From patchwork Mon May 10 09:44:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 93084 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C62AA0548; Mon, 10 May 2021 11:44:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 81CE240140; Mon, 10 May 2021 11:44:15 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 68D5E4003E for ; Mon, 10 May 2021 11:44:14 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14A9Oued013641 for ; Mon, 10 May 2021 02:44:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=WClvi9vJoCF4A04ZKkxm9h0HHrZQ2rkF5QZNkIezn4A=; b=QreXAWTFEjOdiqZU81B+UJzs1iUE4nd4bj359g/19ParuDcZqmA/siZxbLhk73k7f+R/ //tMTAKu3QyOYnIQIg4hlbZp0DoND1XhQtv3O3x6axx0lyJvyUfj9mJAHmZQbqeav+OC 99FMXpXPjG2EktVF9JeWGRbRWFV7xDkL15F4d1Qoi4OVFlDrwMxeH3npE0nI69ZqR8td fUupFRWhRXnXEIh7tD1mQiIvdCnqC+nfyaQip+1ycprEd2ie+bpKFIKk4xJofFYe+oZV vWPhDoM7CjR61QxdFds2lHgB/NaMvz3lBkpE2/ypmVx3h/ZBxMh+1WArPc5zysaYqptf Qg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38eygy8h95-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 10 May 2021 02:44:13 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 10 May 2021 02:44:11 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 10 May 2021 02:44:11 -0700 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 507BA6737A; Mon, 10 May 2021 02:44:07 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal CC: Anoob Joseph , Jerin Jacob , "Ankur Dwivedi" , Tejasree Kondoj , Date: Mon, 10 May 2021 15:14:00 +0530 Message-ID: <1620639840-89-1-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Proofpoint-GUID: jG-E8GemNE_OyhqSDIE_YauVmCgG0m1G X-Proofpoint-ORIG-GUID: jG-E8GemNE_OyhqSDIE_YauVmCgG0m1G X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-10_04:2021-05-10, 2021-05-10 signatures=0 Subject: [dpdk-dev] [PATCH] common/cpt: add checks for offset overflow X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add checks to catch overflow of any offsets. Offset control word specifies, 1. 16 bits encryption offset 2. 8 bits IV offset 3. 8 bits auth offset Signed-off-by: Anoob Joseph Acked-by: Akhil Goyal --- drivers/common/cpt/cpt_ucode.h | 59 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h index 73be980..b8ccbe6 100644 --- a/drivers/common/cpt/cpt_ucode.h +++ b/drivers/common/cpt/cpt_ucode.h @@ -954,6 +954,16 @@ cpt_enc_hmac_prep(uint32_t flags, req->ist.ei2 = (uint64_t)c_vaddr - 8; } + if (unlikely((encr_offset >> 16) || + (iv_offset >> 8) || + (auth_offset >> 8))) { + CPT_LOG_DP_ERR("Offset not supported"); + CPT_LOG_DP_ERR("enc_offset: %d", encr_offset); + CPT_LOG_DP_ERR("iv_offset : %d", iv_offset); + CPT_LOG_DP_ERR("auth_offset: %d", auth_offset); + return; + } + /* 16 byte aligned cpt res address */ req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); *req->completion_addr = COMPLETION_CODE_INIT; @@ -1116,6 +1126,16 @@ cpt_dec_hmac_prep(uint32_t flags, dest[1] = src[1]; } + if (unlikely((encr_offset >> 16) || + (iv_offset >> 8) || + (auth_offset >> 8))) { + CPT_LOG_DP_ERR("Offset not supported"); + CPT_LOG_DP_ERR("enc_offset: %d", encr_offset); + CPT_LOG_DP_ERR("iv_offset : %d", iv_offset); + CPT_LOG_DP_ERR("auth_offset: %d", auth_offset); + return; + } + *(uint64_t *)offset_vaddr = rte_cpu_to_be_64(((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) | @@ -1144,6 +1164,16 @@ cpt_dec_hmac_prep(uint32_t flags, dest[1] = src[1]; } + if (unlikely((encr_offset >> 16) || + (iv_offset >> 8) || + (auth_offset >> 8))) { + CPT_LOG_DP_ERR("Offset not supported"); + CPT_LOG_DP_ERR("enc_offset: %d", encr_offset); + CPT_LOG_DP_ERR("iv_offset : %d", iv_offset); + CPT_LOG_DP_ERR("auth_offset: %d", auth_offset); + return; + } + *(uint64_t *)offset_vaddr = rte_cpu_to_be_64(((uint64_t)encr_offset << 16) | ((uint64_t)iv_offset << 8) | @@ -1401,6 +1431,14 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags, offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16); } + if (unlikely((encr_offset >> 16) || + (auth_offset >> 8))) { + CPT_LOG_DP_ERR("Offset not supported"); + CPT_LOG_DP_ERR("enc_offset: %d", encr_offset); + CPT_LOG_DP_ERR("auth_offset: %d", auth_offset); + return; + } + /* IV */ iv_s = (flags == 0x1) ? params->auth_iv_buf : params->iv_buf; @@ -1809,6 +1847,12 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags, req->ist.ei2 = (uint64_t)c_vaddr - 8; } + if (unlikely((encr_offset >> 16))) { + CPT_LOG_DP_ERR("Offset not supported"); + CPT_LOG_DP_ERR("enc_offset: %d", encr_offset); + return; + } + /* 16 byte aligned cpt res address */ req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr); *req->completion_addr = COMPLETION_CODE_INIT; @@ -1924,11 +1968,21 @@ cpt_kasumi_enc_prep(uint32_t req_flags, outputlen = inputlen; /* iv offset is 0 */ *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16); + if (unlikely((encr_offset >> 16))) { + CPT_LOG_DP_ERR("Offset not supported"); + CPT_LOG_DP_ERR("enc_offset: %d", encr_offset); + return; + } } else { inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8); outputlen = mac_len; /* iv offset is 0 */ *offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset); + if (unlikely((auth_offset >> 8))) { + CPT_LOG_DP_ERR("Offset not supported"); + CPT_LOG_DP_ERR("auth_offset: %d", auth_offset); + return; + } } i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr, @@ -2120,6 +2174,11 @@ cpt_kasumi_dec_prep(uint64_t d_offs, /* Offset control word followed by iv */ *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16); + if (unlikely((encr_offset >> 16))) { + CPT_LOG_DP_ERR("Offset not supported"); + CPT_LOG_DP_ERR("enc_offset: %d", encr_offset); + return; + } i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr, OFF_CTRL_LEN + iv_len);