From patchwork Fri Dec 17 09:19:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 105219 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0AA64A0352; Fri, 17 Dec 2021 10:22:12 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7BECB41155; Fri, 17 Dec 2021 10:21:30 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D2A8841174 for ; Fri, 17 Dec 2021 10:21:28 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BH3tbd1003992 for ; Fri, 17 Dec 2021 01:21:28 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=OwAl1IyJ9/3Uo9BFVRXvppn3kiUfiXOXbbZMbE3eOLI=; b=Uud7PhDnRyWCsyg/Ea9AJu0MdxdYyMRVeWQwb7QADarrAdCW1mJZQWT0fh9IMbrawaXr 7r/BG7SW2M+JjVdkWy0agzoJLuzEHCMRnb8WGk9jVfBkynHK7oKIoMEmyRJr2TE2avTg 3QPlu9j/uutQOJEnPrrNajKl4r5+0n24yWP/c8z5maHmAOH/TMGb/onvVMSI02z3GGQr EW1uhVUpFkSc/HeCUVx4EoKi3TMBBoTtL4cXuiNLxFWDJ9knFKNEnkY6R/b/tdjyJ/fe ck8B9uLDPF1j1t7VTZUc/LcF5CRyhFP8jK3J08vhPm4v0fShSMkRScCjye4ekaWJig6G sQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3d0b362s81-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 17 Dec 2021 01:21:27 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 17 Dec 2021 01:21:26 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 17 Dec 2021 01:21:26 -0800 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 9DDA93F70A5; Fri, 17 Dec 2021 01:21:24 -0800 (PST) From: Anoob Joseph To: Akhil Goyal , Jerin Jacob CC: Tejasree Kondoj , Archana Muniganti , Subject: [PATCH v3 17/29] crypto/cnxk: add context reload for IV Date: Fri, 17 Dec 2021 14:49:59 +0530 Message-ID: <1639732811-1440-18-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1639732811-1440-1-git-send-email-anoobj@marvell.com> References: <1639676975-1316-1-git-send-email-anoobj@marvell.com> <1639732811-1440-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: YmQeJTxivyihHxkWAclk6N1m7qUz8tpx X-Proofpoint-GUID: YmQeJTxivyihHxkWAclk6N1m7qUz8tpx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-17_03,2021-12-16_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Tejasree Kondoj Adding context reload in datapath for IV in debug mode. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 7 ++++--- drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 10 ++++++++-- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 7617bdc..638268e 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -49,7 +49,8 @@ cn10k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op) } static __rte_always_inline int __rte_hot -cpt_sec_inst_fill(struct rte_crypto_op *op, struct cn10k_sec_session *sess, +cpt_sec_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, + struct cn10k_sec_session *sess, struct cpt_inflight_req *infl_req, struct cpt_inst_s *inst) { struct rte_crypto_sym_op *sym_op = op->sym; @@ -69,7 +70,7 @@ cpt_sec_inst_fill(struct rte_crypto_op *op, struct cn10k_sec_session *sess, sa = &sess->sa; if (sa->is_outbound) - ret = process_outb_sa(op, sa, inst); + ret = process_outb_sa(&qp->lf, op, sa, inst); else { infl_req->op_flags |= CPT_OP_FLAGS_IPSEC_DIR_INBOUND; ret = process_inb_sa(op, sa, inst); @@ -122,7 +123,7 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[], if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) { sec_sess = get_sec_session_private_data( sym_op->sec_session); - ret = cpt_sec_inst_fill(op, sec_sess, infl_req, + ret = cpt_sec_inst_fill(qp, op, sec_sess, infl_req, &inst[0]); if (unlikely(ret)) return 0; diff --git a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h index cab6a50..f2d8122 100644 --- a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h +++ b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h @@ -48,8 +48,8 @@ ipsec_po_sa_aes_gcm_iv_set(struct cn10k_ipsec_sa *sess, } static __rte_always_inline int -process_outb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sess, - struct cpt_inst_s *inst) +process_outb_sa(struct roc_cpt_lf *lf, struct rte_crypto_op *cop, + struct cn10k_ipsec_sa *sess, struct cpt_inst_s *inst) { struct rte_crypto_sym_op *sym_op = cop->sym; struct rte_mbuf *m_src = sym_op->m_src; @@ -61,6 +61,8 @@ process_outb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sess, return -ENOMEM; } + RTE_SET_USED(lf); + #ifdef LA_IPSEC_DEBUG if (sess->out_sa.w2.s.iv_src == ROC_IE_OT_SA_IV_SRC_FROM_SA) { if (sess->out_sa.w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM) @@ -68,6 +70,10 @@ process_outb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sess, else ipsec_po_sa_iv_set(sess, cop); } + + /* Trigger CTX reload to fetch new data from DRAM */ + roc_cpt_lf_ctx_reload(lf, &sess->out_sa); + rte_delay_ms(1); #endif if (m_src->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)