From patchwork Wed Apr 27 18:17:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 110383 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CC12EA0093; Wed, 27 Apr 2022 20:22:53 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9DB414280D; Wed, 27 Apr 2022 20:22:37 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 917644113F for ; Wed, 27 Apr 2022 20:22:34 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651083754; x=1682619754; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=jCTOJYu9z22R0Wrz+hlEe5fsrFvRhkLNrXC26sQIuUE=; b=gK786UtKCF9t48C/p+Zet0PMiUHrcN7OJAadXDB9Cs/S+3NpsP6FLIwz AXy2s2aRSE0flNw0CXYgKHor4mou01zuc/eX2CjJcGPUHoh/cqrtoU9LW 3PQuK1YFeYT2Kdn6F7Qah1WOwDSqqUHgGxbpC9ZGxW0DmngGFii7xEauT Ol5fUQO/gzxLS9bm/+OzP2Oe7afwrJfKvQsnqu9xRytD3bwEEsj3bwytb H9ZhmxmADZ1wQ43i+1PqRBb6sSC9efBdLxWsg1bVBBCxzZsaRVmJWYZd5 1G4i+CgDX5coa6MI83gkFwM79L5N+CI7sOkTVXLVekFNWkIBpAOAfJBI/ A==; X-IronPort-AV: E=McAfee;i="6400,9594,10330"; a="246587337" X-IronPort-AV: E=Sophos;i="5.90,293,1643702400"; d="scan'208";a="246587337" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2022 11:22:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,293,1643702400"; d="scan'208";a="730937308" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga005.jf.intel.com with ESMTP; 27 Apr 2022 11:22:29 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com Cc: trix@redhat.com, thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, mingshan.zhang@intel.com, david.marchand@redhat.com, Nicolas Chautru Subject: [PATCH v2 4/5] baseband/acc100: start explicitly PF Monitor from PMD Date: Wed, 27 Apr 2022 11:17:02 -0700 Message-Id: <1651083423-33202-5-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1651083423-33202-1-git-send-email-nicolas.chautru@intel.com> References: <1651083423-33202-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Ensure the performance monitor is restarted in case this is reset after VF FLR. Signed-off-by: Nicolas Chautru --- drivers/baseband/acc100/rte_acc100_pmd.c | 4 ++++ drivers/baseband/acc100/rte_acc100_pmd.h | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index b03cedc..b588f5f 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -263,6 +263,10 @@ & 0xF; } + /* Start Pmon */ + acc100_reg_write(d, reg_addr->pmon_ctrl_a, 0x2); + acc100_reg_write(d, reg_addr->pmon_ctrl_b, 0x2); + /* Read PF mode */ if (d->pf_device) { reg_mode = acc100_reg_read(d, HWPfHiPfMode); diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h index 6438031..f126cc0 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.h +++ b/drivers/baseband/acc100/rte_acc100_pmd.h @@ -475,6 +475,8 @@ struct acc100_registry_addr { unsigned int depth_log1_offset; unsigned int qman_group_func; unsigned int ddr_range; + unsigned int pmon_ctrl_a; + unsigned int pmon_ctrl_b; }; /* Structure holding registry addresses for PF */ @@ -504,6 +506,8 @@ struct acc100_registry_addr { .depth_log1_offset = HWPfQmgrGrpDepthLog21Vf, .qman_group_func = HWPfQmgrGrpFunction0, .ddr_range = HWPfDmaVfDdrBaseRw, + .pmon_ctrl_a = HWPfPermonACntrlRegVf, + .pmon_ctrl_b = HWPfPermonBCntrlRegVf, }; /* Structure holding registry addresses for VF */ @@ -533,6 +537,8 @@ struct acc100_registry_addr { .depth_log1_offset = HWVfQmgrGrpDepthLog21Vf, .qman_group_func = HWVfQmgrGrpFunction0Vf, .ddr_range = HWVfDmaDdrBaseRangeRoVf, + .pmon_ctrl_a = HWVfPmACntrlRegVf, + .pmon_ctrl_b = HWVfPmBCntrlRegVf, }; /* Structure associated with each queue. */