From patchwork Mon Jan 15 06:54:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 33725 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7B133A496; Mon, 15 Jan 2018 08:00:16 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 4F1FAA496 for ; Mon, 15 Jan 2018 08:00:15 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from xuemingl@mellanox.com) with ESMTPS (AES256-SHA encrypted); 15 Jan 2018 09:00:06 +0200 Received: from dev-r630-06.mtbc.labs.mlnx (dev-r630-06.mtbc.labs.mlnx [10.12.205.180]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id w0F7041Y015411; Mon, 15 Jan 2018 09:00:06 +0200 Received: from dev-r630-06.mtbc.labs.mlnx (localhost [127.0.0.1]) by dev-r630-06.mtbc.labs.mlnx (8.14.7/8.14.7) with ESMTP id w0F6sqdQ044126; Mon, 15 Jan 2018 14:54:52 +0800 Received: (from xuemingl@localhost) by dev-r630-06.mtbc.labs.mlnx (8.14.7/8.14.7/Submit) id w0F6sqK5044125; Mon, 15 Jan 2018 14:54:52 +0800 From: Xueming Li To: Nelio Laranjeiro Cc: Xueming Li , Shahaf Shuler , dev@dpdk.org Date: Mon, 15 Jan 2018 14:54:18 +0800 Message-Id: <20180115065420.44065-2-xuemingl@mellanox.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20180115065420.44065-1-xuemingl@mellanox.com> References: <20180115065420.44065-1-xuemingl@mellanox.com> Subject: [dpdk-dev] [PATCH 2/4] net/mlx5: forbid MR registration in secondary process X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Secondary process are not alloed to access verbs resources, add check to prevent MR registration in data path. Signed-off-by: Xueming Li --- doc/guides/nics/mlx5.rst | 1 + drivers/net/mlx5/mlx5_mr.c | 3 +++ drivers/net/mlx5/mlx5_rxtx.h | 3 --- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index bdc2216c0..4373c7990 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -107,6 +107,7 @@ Limitations - Inner RSS for VXLAN frames is not supported yet. - Hardware checksum RX offloads for VXLAN inner header are not supported yet. - Forked secondary process not supported. +- Mempools used in secondary process TX have to be initialized in primary process before rte_eth_dev_start(). - Flow pattern without any specific vlan will match for vlan packets as well: When VLAN spec is not specified in the pattern, the matching rule will be created with VLAN as a wild card. diff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c index 6b29eed55..3c80fbb89 100644 --- a/drivers/net/mlx5/mlx5_mr.c +++ b/drivers/net/mlx5/mlx5_mr.c @@ -278,6 +278,9 @@ priv_mr_new(struct priv *priv, struct rte_mempool *mp) unsigned int i; struct mlx5_mr *mr; + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + rte_panic("Please init mempool before rte_eth_dev_start() in primary process: %s", + mp->name); mr = rte_zmalloc_socket(__func__, sizeof(*mr), 0, mp->socket_id); if (!mr) { DEBUG("unable to configure MR, ibv_reg_mr() failed."); diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 2eb2f0506..18e1d26f3 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -561,9 +561,6 @@ mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb) } if (txq->mp2mr[i]->start <= addr && txq->mp2mr[i]->end >= addr) { - assert(txq->mp2mr[i]->lkey != (uint32_t)-1); - assert(rte_cpu_to_be_32(txq->mp2mr[i]->mr->lkey) == - txq->mp2mr[i]->lkey); txq->mr_cache_idx = i; return txq->mp2mr[i]->lkey; }