From patchwork Tue Aug 27 07:07:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Saxena X-Patchwork-Id: 58024 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 34F971C1DA; Tue, 27 Aug 2019 09:10:44 +0200 (CEST) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id AB6181C034 for ; Tue, 27 Aug 2019 09:09:35 +0200 (CEST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 8B8FC1A001C; Tue, 27 Aug 2019 09:09:35 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 521581A0207; Tue, 27 Aug 2019 09:09:33 +0200 (CEST) Received: from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 3EF3840324; Tue, 27 Aug 2019 15:09:30 +0800 (SGT) From: Sachin Saxena To: dev@dpdk.org Cc: thomas@monjalon.net, Sunil Kumar Kori Date: Tue, 27 Aug 2019 12:37:29 +0530 Message-Id: <20190827070730.11206-30-sachin.saxena@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190827070730.11206-1-sachin.saxena@nxp.com> References: <20190827070730.11206-1-sachin.saxena@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v1 29/30] net/dpaa2: add support for soft parser in MC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Signed-off-by: Sunil Kumar Kori Reviewed-by: Sachin Saxena --- drivers/net/dpaa2/mc/dpni.c | 117 ++++++++++++++++++++++++ drivers/net/dpaa2/mc/fsl_dpni.h | 133 ++++++++++++++++++++++++++++ drivers/net/dpaa2/mc/fsl_dpni_cmd.h | 43 ++++++++- 3 files changed, 292 insertions(+), 1 deletion(-) diff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c index 362cd476f..b37f9976f 100644 --- a/drivers/net/dpaa2/mc/dpni.c +++ b/drivers/net/dpaa2/mc/dpni.c @@ -2484,3 +2484,120 @@ int dpni_get_custom_tpid(struct fsl_mc_io *mc_io, uint32_t cmd_flags, return err; } + +int dpni_load_sw_sequence(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_load_ss_cfg *cfg) +{ + struct dpni_load_sw_sequence *cmd_params; + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_LOAD_SW_SEQUENCE, + cmd_flags, + token); + cmd_params = (struct dpni_load_sw_sequence *)cmd.params; + cmd_params->dest = cfg->dest; + cmd_params->ss_offset = cpu_to_le16(cfg->ss_offset); + cmd_params->ss_size = cpu_to_le16(cfg->ss_size); + cmd_params->ss_iova = cpu_to_le64(cfg->ss_iova); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpni_enable_sw_sequence(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_enable_ss_cfg *cfg) +{ + struct dpni_enable_sw_sequence *cmd_params; + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_ENABLE_SW_SEQUENCE, + cmd_flags, + token); + cmd_params = (struct dpni_enable_sw_sequence *)cmd.params; + cmd_params->dest = cfg->dest; + cmd_params->set_start = cfg->set_start; + cmd_params->hxs = cpu_to_le16(cfg->hxs); + cmd_params->ss_offset = cpu_to_le16(cfg->ss_offset); + cmd_params->param_offset = cfg->param_offset; + cmd_params->param_size = cfg->param_size; + cmd_params->param_iova = cpu_to_le64(cfg->param_iova); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpni_get_sw_sequence_layout() - Get the soft sequence layout + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @src: Source of the layout (WRIOP Rx or Tx) + * @ss_layout_iova: I/O virtual address of 264 bytes DMA-able memory + * + * warning: After calling this function, call dpni_extract_sw_sequence_layout() + * to get the layout. + * + * Return: '0' on Success; error code otherwise. + */ +int dpni_get_sw_sequence_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_soft_sequence_dest src, + uint64_t ss_layout_iova) +{ + struct dpni_get_sw_sequence_layout *cmd_params; + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_SW_SEQUENCE_LAYOUT, + cmd_flags, + token); + + cmd_params = (struct dpni_get_sw_sequence_layout *)cmd.params; + cmd_params->src = src; + cmd_params->layout_iova = cpu_to_le64(ss_layout_iova); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +/** + * dpni_extract_sw_sequence_layout() - extract the software sequence layout + * @layout: software sequence layout + * @sw_sequence_layout_buf: Zeroed 264 bytes of memory before mapping it + * to DMA + * + * This function has to be called after dpni_get_sw_sequence_layout + * + */ +void dpni_extract_sw_sequence_layout(struct dpni_sw_sequence_layout *layout, + const uint8_t *sw_sequence_layout_buf) +{ + const struct dpni_sw_sequence_layout_entry *ext_params; + int i; + uint16_t ss_size, ss_offset; + + ext_params = (const struct dpni_sw_sequence_layout_entry *) + sw_sequence_layout_buf; + + for (i = 0; i < DPNI_SW_SEQUENCE_LAYOUT_SIZE; i++) { + ss_offset = le16_to_cpu(ext_params[i].ss_offset); + ss_size = le16_to_cpu(ext_params[i].ss_size); + + if (ss_offset == 0 && ss_size == 0) { + layout->num_ss = i; + return; + } + + layout->ss[i].ss_offset = ss_offset; + layout->ss[i].ss_size = ss_size; + layout->ss[i].param_offset = ext_params[i].param_offset; + layout->ss[i].param_size = ext_params[i].param_size; + } +} diff --git a/drivers/net/dpaa2/mc/fsl_dpni.h b/drivers/net/dpaa2/mc/fsl_dpni.h index 8b1cfbac7..97fde316e 100644 --- a/drivers/net/dpaa2/mc/fsl_dpni.h +++ b/drivers/net/dpaa2/mc/fsl_dpni.h @@ -96,6 +96,12 @@ struct fsl_mc_io; */ #define DPNI_OPT_CUSTOM_CG 0x000200 + +/** + * Software sequence maximum layout size + */ +#define DPNI_SW_SEQUENCE_LAYOUT_SIZE 33 + int dpni_open(struct fsl_mc_io *mc_io, uint32_t cmd_flags, int dpni_id, @@ -1424,4 +1430,131 @@ struct dpni_custom_tpid_cfg { int dpni_get_custom_tpid(struct fsl_mc_io *mc_io, uint32_t cmd_flags, uint16_t token, struct dpni_custom_tpid_cfg *tpid); +/** + * enum dpni_soft_sequence_dest - Enumeration of WRIOP software sequence + * destinations + * @DPNI_SS_INGRESS: Ingress parser + * @DPNI_SS_EGRESS: Egress parser + */ +enum dpni_soft_sequence_dest { + DPNI_SS_INGRESS = 0, + DPNI_SS_EGRESS = 1, +}; + +/** + * struct dpni_load_ss_cfg - Structure for Software Sequence load configuration + * @dest: Destination of the Software Sequence: ingress or egress parser + * @ss_size: Size of the Software Sequence + * @ss_offset: The offset where to load the Software Sequence (0x20-0x7FD) + * @ss_iova: I/O virtual address of the Software Sequence + */ +struct dpni_load_ss_cfg { + enum dpni_soft_sequence_dest dest; + uint16_t ss_size; + uint16_t ss_offset; + uint64_t ss_iova; +}; + +/** + * struct dpni_enable_ss_cfg - Structure for software sequence enable + * configuration + * @dest: Destination of the Software Sequence: ingress or egress parser + * @hxs: HXS to attach the software sequence to + * @set_start: If the Software Sequence or HDR it is attached to is set as + * parser start + * If hxs=DUMMY_LAST_HXS the ss_offset is set directly as parser + * start else the hdr index code is set as parser start + * @ss_offset: The offset of the Software Sequence to enable or set as parse + * start + * @param_size: Size of the software sequence parameters + * @param_offset: Offset in the parameter zone for the software sequence + * parameters + * @param_iova: I/O virtual address of the parameters + */ +struct dpni_enable_ss_cfg { + enum dpni_soft_sequence_dest dest; + uint16_t hxs; + uint8_t set_start; + uint16_t ss_offset; + uint8_t param_size; + uint8_t param_offset; + uint64_t param_iova; +}; + +/** + * dpni_load_sw_sequence() - Loads a software sequence in parser memory. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Software sequence load configuration + * Return: '0' on Success; Error code otherwise. + */ +int dpni_load_sw_sequence(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_load_ss_cfg *cfg); + +/** + * dpni_eanble_sw_sequence() - Enables a software sequence in the parser + * profile + * corresponding to the ingress or egress of the DPNI. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Software sequence enable configuration + * Return: '0' on Success; Error code otherwise. + */ +int dpni_enable_sw_sequence(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_enable_ss_cfg *cfg); + +/** + * struct dpni_sw_sequence_layout - Structure for software sequence enable + * configuration + * @num_ss: Number of software sequences returned + * @ss: Array of software sequence entries. The number of valid entries + * must match 'num_ss' value + */ +struct dpni_sw_sequence_layout { + uint8_t num_ss; + struct { + uint16_t ss_offset; + uint16_t ss_size; + uint8_t param_offset; + uint8_t param_size; + } ss[DPNI_SW_SEQUENCE_LAYOUT_SIZE]; +}; + +/** + * dpni_get_sw_sequence_layout() - Get the soft sequence layout + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @src: Source of the layout (WRIOP Rx or Tx) + * @ss_layout_iova: I/O virtual address of 264 bytes DMA-able memory + * + * warning: After calling this function, call dpni_extract_sw_sequence_layout() + * to get the layout + * + * Return: '0' on Success; error code otherwise. + */ +int dpni_get_sw_sequence_layout(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + enum dpni_soft_sequence_dest src, + uint64_t ss_layout_iova); + +/** + * dpni_extract_sw_sequence_layout() - extract the software sequence layout + * @layout: software sequence layout + * @sw_sequence_layout_buf: Zeroed 264 bytes of memory before mapping it + * to DMA + * + * This function has to be called after dpni_get_sw_sequence_layout + * + */ +void dpni_extract_sw_sequence_layout(struct dpni_sw_sequence_layout *layout, + const uint8_t *sw_sequence_layout_buf); + #endif /* __FSL_DPNI_H */ diff --git a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h index 5effbb300..dfaccd91c 100644 --- a/drivers/net/dpaa2/mc/fsl_dpni_cmd.h +++ b/drivers/net/dpaa2/mc/fsl_dpni_cmd.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2013-2016 Freescale Semiconductor Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2019 NXP * */ #ifndef _FSL_DPNI_CMD_H @@ -97,6 +97,9 @@ #define DPNI_CMDID_SET_OFFLOAD DPNI_CMD(0x26C) #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE DPNI_CMD(0x266) #define DPNI_CMDID_GET_TX_CONFIRMATION_MODE DPNI_CMD(0x26D) +#define DPNI_CMDID_LOAD_SW_SEQUENCE DPNI_CMD(0x270) +#define DPNI_CMDID_ENABLE_SW_SEQUENCE DPNI_CMD(0x271) +#define DPNI_CMDID_GET_SW_SEQUENCE_LAYOUT DPNI_CMD(0x272) #define DPNI_CMDID_SET_OPR DPNI_CMD(0x26e) #define DPNI_CMDID_GET_OPR DPNI_CMD(0x26f) #define DPNI_CMDID_SET_RX_FS_DIST DPNI_CMD(0x273) @@ -798,5 +801,43 @@ struct dpni_cmd_set_rx_hash_dist { uint64_t key_cfg_iova; }; +struct dpni_load_sw_sequence { + uint8_t dest; + uint8_t pad0[7]; + uint16_t ss_offset; + uint16_t pad1; + uint16_t ss_size; + uint16_t pad2; + uint64_t ss_iova; +}; + +struct dpni_enable_sw_sequence { + uint8_t dest; + uint8_t pad0[7]; + uint16_t ss_offset; + uint16_t hxs; + uint8_t set_start; + uint8_t pad1[3]; + uint8_t param_offset; + uint8_t pad2[3]; + uint8_t param_size; + uint8_t pad3[3]; + uint64_t param_iova; +}; + +struct dpni_get_sw_sequence_layout { + uint8_t src; + uint8_t pad0[7]; + uint64_t layout_iova; +}; + +struct dpni_sw_sequence_layout_entry { + uint16_t ss_offset; + uint16_t ss_size; + uint8_t param_offset; + uint8_t param_size; + uint16_t pad; +}; + #pragma pack(pop) #endif /* _FSL_DPNI_CMD_H */