diff mbox series

[v2,5/5] config: add Arm Neoverse N2

Message ID 20210108082523.1062058-6-ruifeng.wang@arm.com (mailing list archive)
State Superseded, archived
Delegated to: David Marchand
Headers
Series lpm lookup with sve support |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-abi-testing success Testing PASS
ci/iol-testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Functional fail Functional Testing issues
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS

Commit Message

Ruifeng Wang Jan. 8, 2021, 8:25 a.m. UTC 
  Add Arm Neoverse N2 cpu support.

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
 config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++
 config/arm/meson.build        | 11 ++++++++++-
 2 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_n2_linux_gcc

Comments

Honnappa Nagarahalli Jan. 8, 2021, 11:58 p.m. UTC | #1 
+ Juraj

Please note that this clashes with Juraj's patch for meson rework.

<snip>

> 
> Add Arm Neoverse N2 cpu support.
> 
> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> ---
>  config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++
>  config/arm/meson.build        | 11 ++++++++++-
>  2 files changed, 27 insertions(+), 1 deletion(-)  create mode 100644
> config/arm/arm64_n2_linux_gcc
> 
> diff --git a/config/arm/arm64_n2_linux_gcc
> b/config/arm/arm64_n2_linux_gcc new file mode 100644 index
> 000000000..78f6f3e2b
> --- /dev/null
> +++ b/config/arm/arm64_n2_linux_gcc
> @@ -0,0 +1,17 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> +pcap-config = ''
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = '0x41'
> +implementor_pn = '0xd49'
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> 42b4e43c7..58e0ae643 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -89,6 +89,14 @@ flags_n1generic_extra = [
>  	['RTE_MAX_NUMA_NODES', 1],
>  	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
>  	['RTE_LIBRTE_VHOST_NUMA', false]]
> +flags_n2generic_extra = [
> +	['RTE_MACHINE', '"neoverse-n2"'],
> +	['RTE_MAX_LCORE', 64],
> +	['RTE_CACHE_LINE_SIZE', 64],
> +	['RTE_ARM_FEATURE_ATOMICS', true],
> +	['RTE_USE_C11_MEM_MODEL', true],
> +	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> +	['RTE_LIBRTE_VHOST_NUMA', false]]
Do we need a flag RTE_ARM_FEATURE_SVE?

> 
>  machine_args_generic = [
>  	['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -100,7
> +108,8 @@ machine_args_generic = [
>  	['0xd09', ['-mcpu=cortex-a73']],
>  	['0xd0a', ['-mcpu=cortex-a75']],
>  	['0xd0b', ['-mcpu=cortex-a76']],
> -	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> flags_n1generic_extra]]
> +	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> flags_n1generic_extra],
> +	['0xd49', ['-march=armv8.5-a+crypto+sve'], flags_n2generic_extra]]
Should this be 'sve2'? There should be a flag to indicate SVE2.

> 
>  machine_args_cavium = [
>  	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> --
> 2.25.1
Ruifeng Wang Jan. 11, 2021, 3:01 a.m. UTC | #2 
> -----Original Message-----
> From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Sent: Saturday, January 9, 2021 7:58 AM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; jerinj@marvell.com; Ruifeng
> Wang <Ruifeng.Wang@arm.com>; Jan Viktorin <viktorin@rehivetech.com>;
> Bruce Richardson <bruce.richardson@intel.com>
> Cc: dev@dpdk.org; vladimir.medvedkin@intel.com;
> hemant.agrawal@nxp.com; nd <nd@arm.com>; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; nd <nd@arm.com>
> Subject: RE: [PATCH v2 5/5] config: add Arm Neoverse N2
> 
> + Juraj
> 
> Please note that this clashes with Juraj's patch for meson rework.

Yes. I didn't base it on the build options rework series.
I will rebase when that series got merged.
> 
> <snip>
> 
> >
> > Add Arm Neoverse N2 cpu support.
> >
> > Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> > ---
> >  config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++
> >  config/arm/meson.build        | 11 ++++++++++-
> >  2 files changed, 27 insertions(+), 1 deletion(-)  create mode 100644
> > config/arm/arm64_n2_linux_gcc
> >
> > diff --git a/config/arm/arm64_n2_linux_gcc
> > b/config/arm/arm64_n2_linux_gcc new file mode 100644 index
> > 000000000..78f6f3e2b
> > --- /dev/null
> > +++ b/config/arm/arm64_n2_linux_gcc
> > @@ -0,0 +1,17 @@
> > +[binaries]
> > +c = 'aarch64-linux-gnu-gcc'
> > +cpp = 'aarch64-linux-gnu-cpp'
> > +ar = 'aarch64-linux-gnu-gcc-ar'
> > +strip = 'aarch64-linux-gnu-strip'
> > +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> > +pcap-config = ''
> > +
> > +[host_machine]
> > +system = 'linux'
> > +cpu_family = 'aarch64'
> > +cpu = 'armv8-a'
> > +endian = 'little'
> > +
> > +[properties]
> > +implementor_id = '0x41'
> > +implementor_pn = '0xd49'
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > 42b4e43c7..58e0ae643 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -89,6 +89,14 @@ flags_n1generic_extra = [
> >  	['RTE_MAX_NUMA_NODES', 1],
> >  	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> >  	['RTE_LIBRTE_VHOST_NUMA', false]]
> > +flags_n2generic_extra = [
> > +	['RTE_MACHINE', '"neoverse-n2"'],
> > +	['RTE_MAX_LCORE', 64],
> > +	['RTE_CACHE_LINE_SIZE', 64],
> > +	['RTE_ARM_FEATURE_ATOMICS', true],
> > +	['RTE_USE_C11_MEM_MODEL', true],
> > +	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > +	['RTE_LIBRTE_VHOST_NUMA', false]]
> Do we need a flag RTE_ARM_FEATURE_SVE?

I don't think extra flag is needed. We can rely on __ARM_FEATURE_SVE from compiler.
One scenario I can think of where RTE_ARM_FEATURE_SVE can be needed is, when we are
writing inline assembly with sve instructions and using compiler that has no sve support.
I'm not sure we will have sve inline assembly as C intrinsics are available.
> 
> >
> >  machine_args_generic = [
> >  	['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -100,7
> > +108,8 @@ machine_args_generic = [
> >  	['0xd09', ['-mcpu=cortex-a73']],
> >  	['0xd0a', ['-mcpu=cortex-a75']],
> >  	['0xd0b', ['-mcpu=cortex-a76']],
> > -	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > flags_n1generic_extra]]
> > +	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > flags_n1generic_extra],
> > +	['0xd49', ['-march=armv8.5-a+crypto+sve'], flags_n2generic_extra]]
> Should this be 'sve2'? There should be a flag to indicate SVE2.

Yes. N2 supports sve2 and sve2 is superset of sve.
I will do the change in next version.
> 
> >
> >  machine_args_cavium = [
> >  	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > --
> > 2.25.1
Jerin Jacob Jan. 11, 2021, 3:09 a.m. UTC | #3 
On Mon, Jan 11, 2021 at 8:31 AM Ruifeng Wang <Ruifeng.Wang@arm.com> wrote:
>
>
> > -----Original Message-----
> > From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> > Sent: Saturday, January 9, 2021 7:58 AM
> > To: Ruifeng Wang <Ruifeng.Wang@arm.com>; jerinj@marvell.com; Ruifeng
> > Wang <Ruifeng.Wang@arm.com>; Jan Viktorin <viktorin@rehivetech.com>;
> > Bruce Richardson <bruce.richardson@intel.com>
> > Cc: dev@dpdk.org; vladimir.medvedkin@intel.com;
> > hemant.agrawal@nxp.com; nd <nd@arm.com>; Honnappa Nagarahalli
> > <Honnappa.Nagarahalli@arm.com>; nd <nd@arm.com>
> > Subject: RE: [PATCH v2 5/5] config: add Arm Neoverse N2
> >
> > + Juraj
> >
> > Please note that this clashes with Juraj's patch for meson rework.
>
> Yes. I didn't base it on the build options rework series.
> I will rebase when that series got merged.
> >
> > <snip>
> >
> > >
> > > Add Arm Neoverse N2 cpu support.
> > >
> > > Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> > > ---
> > >  config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++
> > >  config/arm/meson.build        | 11 ++++++++++-
> > >  2 files changed, 27 insertions(+), 1 deletion(-)  create mode 100644
> > > config/arm/arm64_n2_linux_gcc
> > >
> > > diff --git a/config/arm/arm64_n2_linux_gcc
> > > b/config/arm/arm64_n2_linux_gcc new file mode 100644 index
> > > 000000000..78f6f3e2b
> > > --- /dev/null
> > > +++ b/config/arm/arm64_n2_linux_gcc
> > > @@ -0,0 +1,17 @@
> > > +[binaries]
> > > +c = 'aarch64-linux-gnu-gcc'
> > > +cpp = 'aarch64-linux-gnu-cpp'
> > > +ar = 'aarch64-linux-gnu-gcc-ar'
> > > +strip = 'aarch64-linux-gnu-strip'
> > > +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> > > +pcap-config = ''
> > > +
> > > +[host_machine]
> > > +system = 'linux'
> > > +cpu_family = 'aarch64'
> > > +cpu = 'armv8-a'
> > > +endian = 'little'
> > > +
> > > +[properties]
> > > +implementor_id = '0x41'
> > > +implementor_pn = '0xd49'
> > > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > > 42b4e43c7..58e0ae643 100644
> > > --- a/config/arm/meson.build
> > > +++ b/config/arm/meson.build
> > > @@ -89,6 +89,14 @@ flags_n1generic_extra = [
> > >     ['RTE_MAX_NUMA_NODES', 1],
> > >     ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > >     ['RTE_LIBRTE_VHOST_NUMA', false]]
> > > +flags_n2generic_extra = [
> > > +   ['RTE_MACHINE', '"neoverse-n2"'],
> > > +   ['RTE_MAX_LCORE', 64],
> > > +   ['RTE_CACHE_LINE_SIZE', 64],
> > > +   ['RTE_ARM_FEATURE_ATOMICS', true],
> > > +   ['RTE_USE_C11_MEM_MODEL', true],
> > > +   ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > > +   ['RTE_LIBRTE_VHOST_NUMA', false]]
> > Do we need a flag RTE_ARM_FEATURE_SVE?
>
> I don't think extra flag is needed. We can rely on __ARM_FEATURE_SVE from compiler.
> One scenario I can think of where RTE_ARM_FEATURE_SVE can be needed is, when we are
> writing inline assembly with sve instructions and using compiler that has no sve support.
> I'm not sure we will have sve inline assembly as C intrinsics are available.

It may be useful to introduce RTE_ARM_FEATURE_SVE to abstract any
compiler difference in
future(GCC vs clang or another tool chain etc).


> >
> > >
> > >  machine_args_generic = [
> > >     ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -100,7
> > > +108,8 @@ machine_args_generic = [
> > >     ['0xd09', ['-mcpu=cortex-a73']],
> > >     ['0xd0a', ['-mcpu=cortex-a75']],
> > >     ['0xd0b', ['-mcpu=cortex-a76']],
> > > -   ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > > flags_n1generic_extra]]
> > > +   ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > > flags_n1generic_extra],
> > > +   ['0xd49', ['-march=armv8.5-a+crypto+sve'], flags_n2generic_extra]]
> > Should this be 'sve2'? There should be a flag to indicate SVE2.
>
> Yes. N2 supports sve2 and sve2 is superset of sve.
> I will do the change in next version.
> >
> > >
> > >  machine_args_cavium = [
> > >     ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > > --
> > > 2.25.1
>
Ruifeng Wang Jan. 11, 2021, 8:32 a.m. UTC | #4 
> -----Original Message-----
> From: Jerin Jacob <jerinjacobk@gmail.com>
> Sent: Monday, January 11, 2021 11:09 AM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>
> Cc: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>;
> jerinj@marvell.com; Jan Viktorin <viktorin@rehivetech.com>; Bruce
> Richardson <bruce.richardson@intel.com>; dev@dpdk.org;
> vladimir.medvedkin@intel.com; hemant.agrawal@nxp.com; nd
> <nd@arm.com>
> Subject: Re: [dpdk-dev] [PATCH v2 5/5] config: add Arm Neoverse N2
> 
> On Mon, Jan 11, 2021 at 8:31 AM Ruifeng Wang <Ruifeng.Wang@arm.com>
> wrote:
> >
> >
> > > -----Original Message-----
> > > From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> > > Sent: Saturday, January 9, 2021 7:58 AM
> > > To: Ruifeng Wang <Ruifeng.Wang@arm.com>; jerinj@marvell.com;
> Ruifeng
> > > Wang <Ruifeng.Wang@arm.com>; Jan Viktorin
> <viktorin@rehivetech.com>;
> > > Bruce Richardson <bruce.richardson@intel.com>
> > > Cc: dev@dpdk.org; vladimir.medvedkin@intel.com;
> > > hemant.agrawal@nxp.com; nd <nd@arm.com>; Honnappa Nagarahalli
> > > <Honnappa.Nagarahalli@arm.com>; nd <nd@arm.com>
> > > Subject: RE: [PATCH v2 5/5] config: add Arm Neoverse N2
> > >
> > > + Juraj
> > >
> > > Please note that this clashes with Juraj's patch for meson rework.
> >
> > Yes. I didn't base it on the build options rework series.
> > I will rebase when that series got merged.
> > >
> > > <snip>
> > >
> > > >
> > > > Add Arm Neoverse N2 cpu support.
> > > >
> > > > Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> > > > ---
> > > >  config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++
> > > >  config/arm/meson.build        | 11 ++++++++++-
> > > >  2 files changed, 27 insertions(+), 1 deletion(-)  create mode
> > > > 100644 config/arm/arm64_n2_linux_gcc
> > > >
> > > > diff --git a/config/arm/arm64_n2_linux_gcc
> > > > b/config/arm/arm64_n2_linux_gcc new file mode 100644 index
> > > > 000000000..78f6f3e2b
> > > > --- /dev/null
> > > > +++ b/config/arm/arm64_n2_linux_gcc
> > > > @@ -0,0 +1,17 @@
> > > > +[binaries]
> > > > +c = 'aarch64-linux-gnu-gcc'
> > > > +cpp = 'aarch64-linux-gnu-cpp'
> > > > +ar = 'aarch64-linux-gnu-gcc-ar'
> > > > +strip = 'aarch64-linux-gnu-strip'
> > > > +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> > > > +pcap-config = ''
> > > > +
> > > > +[host_machine]
> > > > +system = 'linux'
> > > > +cpu_family = 'aarch64'
> > > > +cpu = 'armv8-a'
> > > > +endian = 'little'
> > > > +
> > > > +[properties]
> > > > +implementor_id = '0x41'
> > > > +implementor_pn = '0xd49'
> > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > > > 42b4e43c7..58e0ae643 100644
> > > > --- a/config/arm/meson.build
> > > > +++ b/config/arm/meson.build
> > > > @@ -89,6 +89,14 @@ flags_n1generic_extra = [
> > > >     ['RTE_MAX_NUMA_NODES', 1],
> > > >     ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > > >     ['RTE_LIBRTE_VHOST_NUMA', false]]
> > > > +flags_n2generic_extra = [
> > > > +   ['RTE_MACHINE', '"neoverse-n2"'],
> > > > +   ['RTE_MAX_LCORE', 64],
> > > > +   ['RTE_CACHE_LINE_SIZE', 64],
> > > > +   ['RTE_ARM_FEATURE_ATOMICS', true],
> > > > +   ['RTE_USE_C11_MEM_MODEL', true],
> > > > +   ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > > > +   ['RTE_LIBRTE_VHOST_NUMA', false]]
> > > Do we need a flag RTE_ARM_FEATURE_SVE?
> >
> > I don't think extra flag is needed. We can rely on __ARM_FEATURE_SVE
> from compiler.
> > One scenario I can think of where RTE_ARM_FEATURE_SVE can be needed
> > is, when we are writing inline assembly with sve instructions and using
> compiler that has no sve support.
> > I'm not sure we will have sve inline assembly as C intrinsics are available.
> 
> It may be useful to introduce RTE_ARM_FEATURE_SVE to abstract any
> compiler difference in future(GCC vs clang or another tool chain etc).

According to Arm C Language Extension (ACLE) for SVE, preprocessor macros
like __ARM_FEATURE_SVE are defined to indicate available features.
GCC and clang have the macros defined. We can have RTE_ARM_FEATURE_SVE
for some other tool chain that don't stick to ACLE. I'll add in next version.

> 
> 
> > >
> > > >
> > > >  machine_args_generic = [
> > > >     ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@
> > > > -100,7
> > > > +108,8 @@ machine_args_generic = [
> > > >     ['0xd09', ['-mcpu=cortex-a73']],
> > > >     ['0xd0a', ['-mcpu=cortex-a75']],
> > > >     ['0xd0b', ['-mcpu=cortex-a76']],
> > > > -   ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > > > flags_n1generic_extra]]
> > > > +   ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > > > flags_n1generic_extra],
> > > > +   ['0xd49', ['-march=armv8.5-a+crypto+sve'],
> > > > + flags_n2generic_extra]]
> > > Should this be 'sve2'? There should be a flag to indicate SVE2.
> >
> > Yes. N2 supports sve2 and sve2 is superset of sve.
> > I will do the change in next version.
> > >
> > > >
> > > >  machine_args_cavium = [
> > > >     ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > > > --
> > > > 2.25.1
> >
Honnappa Nagarahalli Jan. 11, 2021, 1:58 p.m. UTC | #5 
<snip>

> > > >
> > > > + Juraj
> > > >
> > > > Please note that this clashes with Juraj's patch for meson rework.
> > >
> > > Yes. I didn't base it on the build options rework series.
> > > I will rebase when that series got merged.
> > > >
> > > > <snip>
> > > >
> > > > >
> > > > > Add Arm Neoverse N2 cpu support.
> > > > >
> > > > > Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
> > > > > ---
> > > > >  config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++
> > > > >  config/arm/meson.build        | 11 ++++++++++-
> > > > >  2 files changed, 27 insertions(+), 1 deletion(-)  create mode
> > > > > 100644 config/arm/arm64_n2_linux_gcc
> > > > >
> > > > > diff --git a/config/arm/arm64_n2_linux_gcc
> > > > > b/config/arm/arm64_n2_linux_gcc new file mode 100644 index
> > > > > 000000000..78f6f3e2b
> > > > > --- /dev/null
> > > > > +++ b/config/arm/arm64_n2_linux_gcc
> > > > > @@ -0,0 +1,17 @@
> > > > > +[binaries]
> > > > > +c = 'aarch64-linux-gnu-gcc'
> > > > > +cpp = 'aarch64-linux-gnu-cpp'
> > > > > +ar = 'aarch64-linux-gnu-gcc-ar'
> > > > > +strip = 'aarch64-linux-gnu-strip'
> > > > > +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> > > > > +pcap-config = ''
> > > > > +
> > > > > +[host_machine]
> > > > > +system = 'linux'
> > > > > +cpu_family = 'aarch64'
> > > > > +cpu = 'armv8-a'
> > > > > +endian = 'little'
> > > > > +
> > > > > +[properties]
> > > > > +implementor_id = '0x41'
> > > > > +implementor_pn = '0xd49'
> > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build
> > > > > index
> > > > > 42b4e43c7..58e0ae643 100644
> > > > > --- a/config/arm/meson.build
> > > > > +++ b/config/arm/meson.build
> > > > > @@ -89,6 +89,14 @@ flags_n1generic_extra = [
> > > > >     ['RTE_MAX_NUMA_NODES', 1],
> > > > >     ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > > > >     ['RTE_LIBRTE_VHOST_NUMA', false]]
> > > > > +flags_n2generic_extra = [
> > > > > +   ['RTE_MACHINE', '"neoverse-n2"'],
> > > > > +   ['RTE_MAX_LCORE', 64],
> > > > > +   ['RTE_CACHE_LINE_SIZE', 64],
> > > > > +   ['RTE_ARM_FEATURE_ATOMICS', true],
> > > > > +   ['RTE_USE_C11_MEM_MODEL', true],
> > > > > +   ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> > > > > +   ['RTE_LIBRTE_VHOST_NUMA', false]]
> > > > Do we need a flag RTE_ARM_FEATURE_SVE?
> > >
> > > I don't think extra flag is needed. We can rely on __ARM_FEATURE_SVE
> > from compiler.
> > > One scenario I can think of where RTE_ARM_FEATURE_SVE can be needed
> > > is, when we are writing inline assembly with sve instructions and
> > > using
> > compiler that has no sve support.
> > > I'm not sure we will have sve inline assembly as C intrinsics are available.
> >
> > It may be useful to introduce RTE_ARM_FEATURE_SVE to abstract any
> > compiler difference in future(GCC vs clang or another tool chain etc).
> 
> According to Arm C Language Extension (ACLE) for SVE, preprocessor macros
> like __ARM_FEATURE_SVE are defined to indicate available features.
> GCC and clang have the macros defined. We can have RTE_ARM_FEATURE_SVE
> for some other tool chain that don't stick to ACLE. I'll add in next version.
The flag __ARM_FEATURE_SVE is a requirement from ACLE. If it is not defined, it is a bug in the compiler. Since, GCC/Clang define this flag, I am thinking we are fine without defining our own. It avoids checking for this additional flag in the code. We can always add it when we come across a toolchain that does not define this flag (or fix the toolchain).

BTW, this problem exists for __ARM_FEATURE_ATOMICS, it is not defined by Clang. Hence, we have RTE_ARM_FEATURE_ATOMICS. But, it is getting fixed in Clang.

> 
> >
> >
> > > >
> > > > >
> > > > >  machine_args_generic = [
> > > > >     ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@
> > > > > -100,7
> > > > > +108,8 @@ machine_args_generic = [
> > > > >     ['0xd09', ['-mcpu=cortex-a73']],
> > > > >     ['0xd0a', ['-mcpu=cortex-a75']],
> > > > >     ['0xd0b', ['-mcpu=cortex-a76']],
> > > > > -   ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > > > > flags_n1generic_extra]]
> > > > > +   ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> > > > > flags_n1generic_extra],
> > > > > +   ['0xd49', ['-march=armv8.5-a+crypto+sve'],
> > > > > + flags_n2generic_extra]]
> > > > Should this be 'sve2'? There should be a flag to indicate SVE2.
> > >
> > > Yes. N2 supports sve2 and sve2 is superset of sve.
> > > I will do the change in next version.
> > > >
> > > > >
> > > > >  machine_args_cavium = [
> > > > >     ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> > > > > --
> > > > > 2.25.1
> > >
diff mbox series

Patch

diff --git a/config/arm/arm64_n2_linux_gcc b/config/arm/arm64_n2_linux_gcc
new file mode 100644
index 000000000..78f6f3e2b
--- /dev/null
+++ b/config/arm/arm64_n2_linux_gcc
@@ -0,0 +1,17 @@ 
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x41'
+implementor_pn = '0xd49'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 42b4e43c7..58e0ae643 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -89,6 +89,14 @@  flags_n1generic_extra = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
 	['RTE_LIBRTE_VHOST_NUMA', false]]
+flags_n2generic_extra = [
+	['RTE_MACHINE', '"neoverse-n2"'],
+	['RTE_MAX_LCORE', 64],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_ARM_FEATURE_ATOMICS', true],
+	['RTE_USE_C11_MEM_MODEL', true],
+	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
+	['RTE_LIBRTE_VHOST_NUMA', false]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc', '-moutline-atomics']],
@@ -100,7 +108,8 @@  machine_args_generic = [
 	['0xd09', ['-mcpu=cortex-a73']],
 	['0xd0a', ['-mcpu=cortex-a75']],
 	['0xd0b', ['-mcpu=cortex-a76']],
-	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra]]
+	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra],
+	['0xd49', ['-march=armv8.5-a+crypto+sve'], flags_n2generic_extra]]
 
 machine_args_cavium = [
 	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],