From patchwork Wed Jun 23 04:47:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 94756 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1B031A0C41; Wed, 23 Jun 2021 06:53:52 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BB0A24111C; Wed, 23 Jun 2021 06:50:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id DD0E14111A for ; Wed, 23 Jun 2021 06:50:34 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15N4k7nw025556 for ; Tue, 22 Jun 2021 21:50:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=RrM5xbsPRngvgu7IFOgJJeOunb61vEClrZwfobEa50Q=; b=BWGJaBL1EYrMe4F53raLAzYIgPDeiFPk892af7w3tsSgjRfXnsWxqgxtzneFENmwtyDK tCzpZBpox7jPg04wo9B18/Xct+filSgzjHI71LZmZkIt42OeFWnlY985Q4NXfUl7FmVU lxrfU/iOTOn9M7iF7ohRxNumRTOGQsX5bc1LOv4/3oMpRHbl3GVqp+4G/oIyyHgb2MNy 2f82jYm/7OaYam3Wqm85K4fr3da7i4VF7B3ATOPqZB49Loyl3ZgrqR1Xq91t+wxvQcwm o0upy52BKcVO7DP07q5NPV3nCGWOZCBDu2TcCFXgyiVfISNdD1vJzX+MPKw53+dATevc QQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 39bptj1gx8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 22 Jun 2021 21:50:33 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 22 Jun 2021 21:50:31 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 22 Jun 2021 21:50:31 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B276B5B693E; Tue, 22 Jun 2021 21:50:28 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , , Date: Wed, 23 Jun 2021 10:17:00 +0530 Message-ID: <20210623044702.4240-61-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210623044702.4240-1-ndabilpuram@marvell.com> References: <20210306153404.10781-1-ndabilpuram@marvell.com> <20210623044702.4240-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 0zA3lCaLNYUpQqdlDfU5TWLyPdj0MFfn X-Proofpoint-GUID: 0zA3lCaLNYUpQqdlDfU5TWLyPdj0MFfn X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-23_01:2021-06-22, 2021-06-23 signatures=0 Subject: [dpdk-dev] [PATCH v4 60/62] net/cnxk: added RETA and RSS hash operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satha Rao This patch will implement RETA and RSS hash apis. Also added device argument to lock rx context. Signed-off-by: Satha Rao --- doc/guides/nics/features/cnxk.ini | 2 + doc/guides/nics/features/cnxk_vec.ini | 2 + doc/guides/nics/features/cnxk_vf.ini | 2 + drivers/net/cnxk/cnxk_ethdev.c | 4 ++ drivers/net/cnxk/cnxk_ethdev.h | 10 +++ drivers/net/cnxk/cnxk_ethdev_devargs.c | 4 ++ drivers/net/cnxk/cnxk_ethdev_ops.c | 121 +++++++++++++++++++++++++++++++++ 7 files changed, 145 insertions(+) diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index 5874531..9945af9 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -23,6 +23,8 @@ Promiscuous mode = Y Allmulticast mode = Y Unicast MAC filter = Y RSS hash = Y +RSS key update = Y +RSS reta update = Y Inner RSS = Y Flow control = Y Jumbo frame = Y diff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini index 4871fac..77d63c4 100644 --- a/doc/guides/nics/features/cnxk_vec.ini +++ b/doc/guides/nics/features/cnxk_vec.ini @@ -22,6 +22,8 @@ Promiscuous mode = Y Allmulticast mode = Y Unicast MAC filter = Y RSS hash = Y +RSS key update = Y +RSS reta update = Y Inner RSS = Y Flow control = Y Jumbo frame = Y diff --git a/doc/guides/nics/features/cnxk_vf.ini b/doc/guides/nics/features/cnxk_vf.ini index 81ee7cc..59acfdb 100644 --- a/doc/guides/nics/features/cnxk_vf.ini +++ b/doc/guides/nics/features/cnxk_vf.ini @@ -19,6 +19,8 @@ Queue start/stop = Y MTU update = Y TSO = Y RSS hash = Y +RSS key update = Y +RSS reta update = Y Inner RSS = Y Jumbo frame = Y Scattered Rx = Y diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index b2a8f3a..abd9bf1 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1266,6 +1266,10 @@ struct eth_dev_ops cnxk_eth_dev_ops = { .timesync_write_time = cnxk_nix_timesync_write_time, .timesync_adjust_time = cnxk_nix_timesync_adjust_time, .read_clock = cnxk_nix_read_clock, + .reta_update = cnxk_nix_reta_update, + .reta_query = cnxk_nix_reta_query, + .rss_hash_update = cnxk_nix_rss_hash_update, + .rss_hash_conf_get = cnxk_nix_rss_hash_conf_get, }; static int diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index fa6f16f..cd08e3a 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -330,6 +330,16 @@ uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev); /* RSS */ uint32_t cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t ethdev_rss, uint8_t rss_level); +int cnxk_nix_reta_update(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); +int cnxk_nix_reta_query(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size); +int cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_conf *rss_conf); +int cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_conf *rss_conf); /* Link */ void cnxk_nix_toggle_flag_link_cfg(struct cnxk_eth_dev *dev, bool set); diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index 7fd06eb..c76b628 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -109,6 +109,7 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args) #define CNXK_FLOW_MAX_PRIORITY "flow_max_priority" #define CNXK_SWITCH_HEADER_TYPE "switch_header" #define CNXK_RSS_TAG_AS_XOR "tag_as_xor" +#define CNXK_LOCK_RX_CTX "lock_rx_ctx" int cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) @@ -120,6 +121,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) uint16_t flow_max_priority = 3; uint16_t rss_tag_as_xor = 0; uint16_t scalar_enable = 0; + uint8_t lock_rx_ctx = 0; struct rte_kvargs *kvlist; if (devargs == NULL) @@ -143,6 +145,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) &parse_switch_header_type, &switch_header_type); rte_kvargs_process(kvlist, CNXK_RSS_TAG_AS_XOR, &parse_flag, &rss_tag_as_xor); + rte_kvargs_process(kvlist, CNXK_LOCK_RX_CTX, &parse_flag, &lock_rx_ctx); rte_kvargs_free(kvlist); null_devargs: @@ -150,6 +153,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev) dev->nix.rss_tag_as_xor = !!rss_tag_as_xor; dev->nix.max_sqb_count = sqb_count; dev->nix.reta_sz = reta_sz; + dev->nix.lock_rx_ctx = lock_rx_ctx; dev->npc.flow_prealloc_size = flow_prealloc_size; dev->npc.flow_max_priority = flow_max_priority; dev->npc.switch_header_type = switch_header_type; diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index 91de6b7..d257763 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -724,3 +724,124 @@ cnxk_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs) return rc; } + +int +cnxk_nix_reta_update(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + uint16_t reta[ROC_NIX_RSS_RETA_MAX]; + struct roc_nix *nix = &dev->nix; + int i, j, rc = -EINVAL, idx = 0; + + if (reta_size != dev->nix.reta_sz) { + plt_err("Size of hash lookup table configured (%d) does not " + "match the number hardware can supported (%d)", + reta_size, dev->nix.reta_sz); + goto fail; + } + + /* Copy RETA table */ + for (i = 0; i < (int)(dev->nix.reta_sz / RTE_RETA_GROUP_SIZE); i++) { + for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { + if ((reta_conf[i].mask >> j) & 0x01) + reta[idx] = reta_conf[i].reta[j]; + idx++; + } + } + + return roc_nix_rss_reta_set(nix, 0, reta); + +fail: + return rc; +} + +int +cnxk_nix_reta_query(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_reta_entry64 *reta_conf, + uint16_t reta_size) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + uint16_t reta[ROC_NIX_RSS_RETA_MAX]; + struct roc_nix *nix = &dev->nix; + int rc = -EINVAL, i, j, idx = 0; + + if (reta_size != dev->nix.reta_sz) { + plt_err("Size of hash lookup table configured (%d) does not " + "match the number hardware can supported (%d)", + reta_size, dev->nix.reta_sz); + goto fail; + } + + rc = roc_nix_rss_reta_get(nix, 0, reta); + if (rc) + goto fail; + + /* Copy RETA table */ + for (i = 0; i < (int)(dev->nix.reta_sz / RTE_RETA_GROUP_SIZE); i++) { + for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { + if ((reta_conf[i].mask >> j) & 0x01) + reta_conf[i].reta[j] = reta[idx]; + idx++; + } + } + + return 0; + +fail: + return rc; +} + +int +cnxk_nix_rss_hash_update(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + uint8_t rss_hash_level; + uint32_t flowkey_cfg; + int rc = -EINVAL; + uint8_t alg_idx; + + if (rss_conf->rss_key && rss_conf->rss_key_len != ROC_NIX_RSS_KEY_LEN) { + plt_err("Hash key size mismatch %d vs %d", + rss_conf->rss_key_len, ROC_NIX_RSS_KEY_LEN); + goto fail; + } + + if (rss_conf->rss_key) + roc_nix_rss_key_set(nix, rss_conf->rss_key); + + rss_hash_level = ETH_RSS_LEVEL(rss_conf->rss_hf); + if (rss_hash_level) + rss_hash_level -= 1; + flowkey_cfg = + cnxk_rss_ethdev_to_nix(dev, rss_conf->rss_hf, rss_hash_level); + + rc = roc_nix_rss_flowkey_set(nix, &alg_idx, flowkey_cfg, + ROC_NIX_RSS_GROUP_DEFAULT, + ROC_NIX_RSS_MCAM_IDX_DEFAULT); + if (rc) { + plt_err("Failed to set RSS hash function rc=%d", rc); + return rc; + } + +fail: + return rc; +} + +int +cnxk_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + + if (rss_conf->rss_key) + roc_nix_rss_key_get(&dev->nix, rss_conf->rss_key); + + rss_conf->rss_key_len = ROC_NIX_RSS_KEY_LEN; + rss_conf->rss_hf = dev->ethdev_rss_hf; + + return 0; +}