diff mbox series

[18/28] net/ice/base: support RSS for GRE tunnel packet

Message ID 20210810025140.1698163-19-qi.z.zhang@intel.com (mailing list archive)
State Accepted
Delegated to: Qi Zhang
Headers show
Series ice: base code update | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Zhang, Qi Z Aug. 10, 2021, 2:51 a.m. UTC
Support RSS of inner headers for GRE tunnel packet.

Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_flow.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

Comments

Junfeng Guo Aug. 10, 2021, 4:42 a.m. UTC | #1
> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:52
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Wu, Wenjun1 <Wenjun1.Wu@intel.com>
> Subject: [PATCH 18/28] net/ice/base: support RSS for GRE tunnel packet
> 
> Support RSS of inner headers for GRE tunnel packet.
> 
> Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
>  drivers/net/ice/base/ice_flow.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
> 
> --
> 2.26.2

Acked-by: Junfeng Guo <junfeng.guo@intel.com>

Regards,
Junfeng Guo
diff mbox series

Patch

diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index b336275d0c..5b26d6c8b2 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -257,7 +257,7 @@  static const u32 ice_ptypes_ipv4_ofos[] = {
  * includes IPV4 other PTYPEs
  */
 static const u32 ice_ptypes_ipv4_ofos_all[] = {
-	0x1D800000, 0x24000800, 0x00000000, 0x00000000,
+	0x1D800000, 0x27BF7800, 0x00000000, 0x00000000,
 	0x00000000, 0x00000155, 0x00000000, 0x00000000,
 	0x00000000, 0x000FC000, 0x83E0FAA0, 0x00000101,
 	0x03FFD500, 0x00000000, 0x00000000, 0x00000000,
@@ -297,7 +297,7 @@  static const u32 ice_ptypes_ipv6_ofos[] = {
  * includes IPV6 other PTYPEs
  */
 static const u32 ice_ptypes_ipv6_ofos_all[] = {
-	0x00000000, 0x00000000, 0x76000000, 0x10002000,
+	0x00000000, 0x00000000, 0x76000000, 0x1EFDE000,
 	0x00000000, 0x000002AA, 0x00000000, 0x00000000,
 	0x00000000, 0x03F00000, 0x7C1F0540, 0x00000206,
 	0xFC002A00, 0x0000003F, 0x00000000, 0x00000000,
@@ -807,7 +807,7 @@  struct ice_flow_prof_params {
 	ICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \
 	ICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP | \
 	ICE_FLOW_SEG_HDR_ECPRI_TP0 | ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0 | \
-	ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP)
+	ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP | ICE_FLOW_SEG_HDR_GRE)
 
 #define ICE_FLOW_SEG_HDRS_L2_MASK	\
 	(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
@@ -1024,11 +1024,9 @@  ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params)
 			ice_and_bitmap(params->ptypes, params->ptypes, src,
 				       ICE_FLOW_PTYPE_MAX);
 		} else if (hdrs & ICE_FLOW_SEG_HDR_GRE) {
-			if (!i) {
-				src = (const ice_bitmap_t *)ice_ptypes_gre_of;
-				ice_and_bitmap(params->ptypes, params->ptypes,
-					       src, ICE_FLOW_PTYPE_MAX);
-			}
+			src = (const ice_bitmap_t *)ice_ptypes_gre_of;
+			ice_and_bitmap(params->ptypes, params->ptypes, src,
+				       ICE_FLOW_PTYPE_MAX);
 		} else if (hdrs & ICE_FLOW_SEG_HDR_GTPC) {
 			src = (const ice_bitmap_t *)ice_ptypes_gtpc;
 			ice_and_bitmap(params->ptypes, params->ptypes,