| Message ID | 20210810025140.1698163-22-qi.z.zhang@intel.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Qi Zhang |
| Headers | show |
| Series | ice: base code update | expand |
| Context | Check | Description |
|---|---|---|
| ci/checkpatch | success | coding style OK |
> -----Original Message----- > From: Zhang, Qi Z <qi.z.zhang@intel.com> > Sent: Tuesday, August 10, 2021 10:52 > To: Yang, Qiming <qiming.yang@intel.com> > Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z > <qi.z.zhang@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com> > Subject: [PATCH 21/28] net/ice/base: enable NVM update reset > capabilities > > Add logic to parse capabilities relating to the firmware update reset > requirements. This includes both capability 0x76, which informs the > driver if the firmware can sometimes skip PCIe resets, and 0x77, which > informs the driver if the firmware might potentially restrict EMP > resets. > > For capability 0x76, if the number is 1, the firmware will report the > required reset level for a given update as part of its response to the > last command sent to program the NVM bank. (Otherwise, if the firmware > does not support this capability then it will always send a 0 in the > field of the response). > > For capability 0x77, if the number is 1, the firmware will report when > EMP reset is available as part of the response to the command for > switching flash banks. (Otherwise, if the firmware does not support this > capability, it will always send a 0 in the field of the response > message). > > These capabilities are required to implement immediate firmware > activation. If the capabilities are set, software can read the response > data and determine what reset level is required to activate the firmware > image. If only an EMP reset is required, and if the EMP reset is not > restricted by firmware, then the driver can issue an EMP reset to > immediately activate the new firmware. > > Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> > Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> > --- > drivers/net/ice/base/ice_common.c | 12 ++++++++++++ > drivers/net/ice/base/ice_type.h | 4 ++++ > 2 files changed, 16 insertions(+) > > -- > 2.26.2 Acked-by: Junfeng Guo <junfeng.guo@intel.com> Regards, Junfeng Guo
diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index a77bf32b1c..2744c3d119 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -2281,6 +2281,18 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", prefix, caps->max_mtu); break; + case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: + caps->pcie_reset_avoidance = (number > 0); + ice_debug(hw, ICE_DBG_INIT, + "%s: pcie_reset_avoidance = %d\n", prefix, + caps->pcie_reset_avoidance); + break; + case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: + caps->reset_restrict_support = (number == 1); + ice_debug(hw, ICE_DBG_INIT, + "%s: reset_restrict_support = %d\n", prefix, + caps->reset_restrict_support); + break; case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0: case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1: case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2: diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index b76404f085..6ae39a345b 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -480,6 +480,10 @@ struct ice_hw_common_caps { #define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0) #define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1) #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) + /* PCIe reset avoidance */ + bool pcie_reset_avoidance; /* false: not supported, true: supported */ + /* Post update reset restriction */ + bool reset_restrict_support; /* false: not supported, true: supported */ /* External topology device images within the NVM */ #define ICE_EXT_TOPO_DEV_IMG_COUNT 4