From patchwork Tue Aug 10 02:51:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 96747 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C9E9FA0C54; Tue, 10 Aug 2021 04:49:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 30B49411AA; Tue, 10 Aug 2021 04:48:54 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 67451410FF for ; Tue, 10 Aug 2021 04:48:52 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10070"; a="214808429" X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="214808429" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2021 19:48:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="483823593" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:48:50 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang , Anirudh Venkataramanan Date: Tue, 10 Aug 2021 10:51:20 +0800 Message-Id: <20210810025140.1698163-9-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210810025140.1698163-1-qi.z.zhang@intel.com> References: <20210810025140.1698163-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 08/28] net/ice/base: print human-friendly PHY types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add functions to print PHY types in human-friendly form Signed-off-by: Anirudh Venkataramanan Signed-off-by: Qi Zhang Acked-by: Junfeng Guo --- drivers/net/ice/base/ice_common.c | 164 ++++++++++++++++++++++++++---- 1 file changed, 146 insertions(+), 18 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index e8d66aad6b..2447d15b87 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -11,6 +11,120 @@ #define ICE_PF_RESET_WAIT_COUNT 300 +/** + * dump_phy_type - helper function that prints PHY type strings + * @hw: pointer to the HW structure + * @phy: 64 bit PHY type to decipher + * @i: bit index within phy + * @phy_string: string corresponding to bit i in phy + * @prefix: prefix string to differentiate multiple dumps + */ +static void +dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string, + const char *prefix) +{ + if (phy & BIT_ULL(i)) + ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i, + phy_string); +} + +/** + * ice_dump_phy_type_low - helper function to dump phy_type_low + * @hw: pointer to the HW structure + * @low: 64 bit value for phy_type_low + * @prefix: prefix string to differentiate multiple dumps + */ +static void +ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix) +{ + ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, + (unsigned long long)low); + + dump_phy_type(hw, low, 0, "100BASE_TX", prefix); + dump_phy_type(hw, low, 1, "100M_SGMII", prefix); + dump_phy_type(hw, low, 2, "1000BASE_T", prefix); + dump_phy_type(hw, low, 3, "1000BASE_SX", prefix); + dump_phy_type(hw, low, 4, "1000BASE_LX", prefix); + dump_phy_type(hw, low, 5, "1000BASE_KX", prefix); + dump_phy_type(hw, low, 6, "1G_SGMII", prefix); + dump_phy_type(hw, low, 7, "2500BASE_T", prefix); + dump_phy_type(hw, low, 8, "2500BASE_X", prefix); + dump_phy_type(hw, low, 9, "2500BASE_KX", prefix); + dump_phy_type(hw, low, 10, "5GBASE_T", prefix); + dump_phy_type(hw, low, 11, "5GBASE_KR", prefix); + dump_phy_type(hw, low, 12, "10GBASE_T", prefix); + dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix); + dump_phy_type(hw, low, 14, "10GBASE_SR", prefix); + dump_phy_type(hw, low, 15, "10GBASE_LR", prefix); + dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix); + dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix); + dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix); + dump_phy_type(hw, low, 19, "25GBASE_T", prefix); + dump_phy_type(hw, low, 20, "25GBASE_CR", prefix); + dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix); + dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix); + dump_phy_type(hw, low, 23, "25GBASE_SR", prefix); + dump_phy_type(hw, low, 24, "25GBASE_LR", prefix); + dump_phy_type(hw, low, 25, "25GBASE_KR", prefix); + dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix); + dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix); + dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix); + dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix); + dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix); + dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix); + dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix); + dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix); + dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix); + dump_phy_type(hw, low, 35, "40G_XLAUI", prefix); + dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix); + dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix); + dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix); + dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix); + dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix); + dump_phy_type(hw, low, 41, "50G_LAUI2", prefix); + dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix); + dump_phy_type(hw, low, 43, "50G_AUI2", prefix); + dump_phy_type(hw, low, 44, "50GBASE_CP", prefix); + dump_phy_type(hw, low, 45, "50GBASE_SR", prefix); + dump_phy_type(hw, low, 46, "50GBASE_FR", prefix); + dump_phy_type(hw, low, 47, "50GBASE_LR", prefix); + dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix); + dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix); + dump_phy_type(hw, low, 50, "50G_AUI1", prefix); + dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix); + dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix); + dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix); + dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix); + dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix); + dump_phy_type(hw, low, 56, "100G_CAUI4", prefix); + dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix); + dump_phy_type(hw, low, 58, "100G_AUI4", prefix); + dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix); + dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix); + dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix); + dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix); + dump_phy_type(hw, low, 63, "100GBASE_DR", prefix); +} + +/** + * ice_dump_phy_type_high - helper function to dump phy_type_high + * @hw: pointer to the HW structure + * @high: 64 bit value for phy_type_high + * @prefix: prefix string to differentiate multiple dumps + */ +static void +ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix) +{ + ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, + (unsigned long long)high); + + dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix); + dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix); + dump_phy_type(hw, high, 2, "100G_CAUI2", prefix); + dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix); + dump_phy_type(hw, high, 4, "100G_AUI2", prefix); +} + /** * ice_set_mac_type - Sets MAC type * @hw: pointer to the HW structure @@ -180,6 +294,7 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, u16 pcaps_size = sizeof(*pcaps); struct ice_aq_desc desc; enum ice_status status; + const char *prefix; struct ice_hw *hw; cmd = &desc.params.get_phy; @@ -200,29 +315,42 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, cmd->param0 |= CPU_TO_LE16(report_mode); status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); - ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", - report_mode); - ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", - (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low)); - ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", - (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high)); - ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); - ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); + + if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) + prefix = "phy_caps_media"; + else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA) + prefix = "phy_caps_no_media"; + else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG) + prefix = "phy_caps_active"; + else if (report_mode == ICE_AQC_REPORT_DFLT_CFG) + prefix = "phy_caps_default"; + else + prefix = "phy_caps_invalid"; + + ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix); + ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix); + + ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", + prefix, report_mode); + ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); + ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, pcaps->low_power_ctrl_an); - ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); - ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, + pcaps->eee_cap); + ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, pcaps->eeer_value); - ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, pcaps->link_fec_options); - ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", - pcaps->module_compliance_enforcement); - ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", - pcaps->extended_compliance_code); - ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", + prefix, pcaps->module_compliance_enforcement); + ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", + prefix, pcaps->extended_compliance_code); + ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, pcaps->module_type[0]); - ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, pcaps->module_type[1]); - ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, pcaps->module_type[2]); if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {