From patchwork Thu Sep 2 02:14:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 97745 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D77A2A0C4C; Thu, 2 Sep 2021 04:18:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 90C4E41104; Thu, 2 Sep 2021 04:17:46 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 95935410FE for ; Thu, 2 Sep 2021 04:17:44 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 181HQ203011573 for ; Wed, 1 Sep 2021 19:17:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=UuPtBQ4Jzvd3UK+/5CxFM8Ry3pLxW/oddD14A88c+Hs=; b=UNARFcr7N1RpEPKe6ch02TR6MLBCADiWINZWdS47qntUQIuLVZCJ16l/Q3MFPH2QEyeF CI7Xib/DmCUmieeg6cfVh9ocgsLGpbul2DeMkIdokSjgue3md1XjLGCRrIcAMHVK9N6w HsBf/ffD1hJX7VYPUumuDxKnAdVH8L4SUJ74gVTeQwAFo4jW2pw6BKqhbR/9ZlKOOohJ AaK6mtm+uCxSB6t59tpUkWSRPIL3U+OHNUzTRfk/DYaIz7mJjmnca509v3Smfu33MRxd jgYVlRjwkQs8YJtUG+Dm5FzGG3cqhC/mJGk1tC33vTG3WKAbL5agpqFSS9L9cMWRL1l4 1A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3atdwq9hu3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 01 Sep 2021 19:17:43 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 1 Sep 2021 19:17:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 1 Sep 2021 19:17:41 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B95753F7040; Wed, 1 Sep 2021 19:17:38 -0700 (PDT) From: Nithin Dabilpuram To: Pavan Nikhilesh , Shijith Thotton , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , , Date: Thu, 2 Sep 2021 07:44:57 +0530 Message-ID: <20210902021505.17607-20-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210902021505.17607-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: iKLyED_EcZb5NX-PZklNP5D7S6EyHlic X-Proofpoint-GUID: iKLyED_EcZb5NX-PZklNP5D7S6EyHlic X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 19/27] net/cnxk: add cn10k Rx support for security offload X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support to receive CPT processed packets on Rx via second pass. Signed-off-by: Nithin Dabilpuram --- drivers/event/cnxk/cn10k_eventdev.c | 80 ++-- drivers/event/cnxk/cn10k_worker.h | 73 +++- drivers/event/cnxk/cn10k_worker_deq.c | 2 +- drivers/event/cnxk/cn10k_worker_deq_burst.c | 2 +- drivers/event/cnxk/cn10k_worker_deq_ca.c | 2 +- drivers/event/cnxk/cn10k_worker_deq_tmo.c | 2 +- drivers/net/cnxk/cn10k_ethdev.h | 4 + drivers/net/cnxk/cn10k_rx.c | 31 +- drivers/net/cnxk/cn10k_rx.h | 648 +++++++++++++++++++++++----- drivers/net/cnxk/cn10k_rx_mseg.c | 2 +- drivers/net/cnxk/cn10k_rx_vec.c | 4 +- drivers/net/cnxk/cn10k_rx_vec_mseg.c | 4 +- drivers/net/cnxk/cn10k_tx.h | 3 - 13 files changed, 688 insertions(+), 169 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index bfb6f1a..2f2e7f8 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -7,7 +7,8 @@ #include "cnxk_worker.h" #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \ - deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \ + deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)] \ + [!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \ [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)] \ [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \ [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)] \ @@ -287,88 +288,91 @@ static void cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev) { struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); - const event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name, + const event_dequeue_t sso_hws_deq[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name, + const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name, + const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t sso_hws_deq_tmo_burst[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name, + const event_dequeue_burst_t + sso_hws_deq_tmo_burst[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_##name, + const event_dequeue_t sso_hws_deq_ca[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t sso_hws_deq_ca_burst[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_burst_##name, + const event_dequeue_burst_t + sso_hws_deq_ca_burst[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name, + const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name, + const event_dequeue_burst_t + sso_hws_deq_seg_burst[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name, + const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name, NIX_RX_FASTPATH_MODES #undef R }; const event_dequeue_burst_t - sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name, + sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; - const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_##name, + const event_dequeue_t sso_hws_deq_ca_seg[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_##name, NIX_RX_FASTPATH_MODES #undef R }; const event_dequeue_burst_t - sso_hws_deq_ca_seg_burst[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_burst_##name, + sso_hws_deq_ca_seg_burst[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_ca_seg_burst_##name, NIX_RX_FASTPATH_MODES #undef R }; @@ -384,7 +388,7 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev) const event_tx_adapter_enqueue sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2] = { -#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \ +#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \ [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_seg_##name, NIX_TX_FASTPATH_MODES #undef T diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index e5ed043..b79bd90 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -106,12 +106,17 @@ cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id, static __rte_always_inline void cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, - void *lookup_mem, void *tstamp) + void *lookup_mem, void *tstamp, uintptr_t lbase) { uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM | (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0); struct rte_event_vector *vec; + uint64_t aura_handle, laddr; uint16_t nb_mbufs, non_vec; + uint16_t lmt_id, d_off; + struct rte_mbuf *mbuf; + uint8_t loff = 0; + uint64_t sa_base; uint64_t **wqe; mbuf_init |= ((uint64_t)port_id) << 48; @@ -121,17 +126,41 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, nb_mbufs = RTE_ALIGN_FLOOR(vec->nb_elem, NIX_DESCS_PER_LOOP); nb_mbufs = cn10k_nix_recv_pkts_vector(&mbuf_init, vec->mbufs, nb_mbufs, flags | NIX_RX_VWQE_F, lookup_mem, - tstamp); + tstamp, lbase); wqe += nb_mbufs; non_vec = vec->nb_elem - nb_mbufs; + if (flags & NIX_RX_OFFLOAD_SECURITY_F && non_vec) { + mbuf = (struct rte_mbuf *)((uintptr_t)wqe[0] - + sizeof(struct rte_mbuf)); + /* Pick first mbuf's aura handle assuming all + * mbufs are from a vec and are from same RQ. + */ + aura_handle = mbuf->pool->pool_id; + ROC_LMT_BASE_ID_GET(lbase, lmt_id); + laddr = lbase; + laddr += 8; + d_off = ((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf); + d_off += (mbuf_init & 0xFFFF); + sa_base = cnxk_nix_sa_base_get(mbuf_init >> 48, lookup_mem); + sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1); + } + while (non_vec) { struct nix_cqe_hdr_s *cqe = (struct nix_cqe_hdr_s *)wqe[0]; - struct rte_mbuf *mbuf; uint64_t tstamp_ptr; mbuf = (struct rte_mbuf *)((char *)cqe - sizeof(struct rte_mbuf)); + + /* Translate meta to mbuf */ + if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + const uint64_t cq_w1 = *((const uint64_t *)cqe + 1); + + mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr, + &loff, mbuf, d_off); + } + cn10k_nix_cqe_to_mbuf(cqe, cqe->tag, mbuf, lookup_mem, mbuf_init, flags); /* Extracting tstamp, if PTP enabled*/ @@ -145,6 +174,12 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags, non_vec--; wqe++; } + + /* Free remaining meta buffers if any */ + if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) { + nix_sec_flush_meta(laddr, lmt_id, loff, aura_handle); + plt_io_wmb(); + } } static __rte_always_inline uint16_t @@ -188,6 +223,34 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev, RTE_EVENT_TYPE_ETHDEV) { uint8_t port = CNXK_SUB_EVENT_FROM_TAG(gw.u64[0]); + if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + struct rte_mbuf *m; + uintptr_t sa_base; + uint64_t iova = 0; + uint8_t loff = 0; + uint16_t d_off; + uint64_t cq_w1; + + m = (struct rte_mbuf *)mbuf; + d_off = (uintptr_t)(m->buf_addr) - (uintptr_t)m; + d_off += RTE_PKTMBUF_HEADROOM; + + cq_w1 = *(uint64_t *)(gw.u64[1] + 8); + + sa_base = cnxk_nix_sa_base_get(port, + lookup_mem); + sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1); + + mbuf = (uint64_t)nix_sec_meta_to_mbuf_sc(cq_w1, + sa_base, (uintptr_t)&iova, + &loff, (struct rte_mbuf *)mbuf, + d_off); + if (loff) + roc_npa_aura_op_free(m->pool->pool_id, + 0, iova); + + } + gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]); cn10k_wqe_to_mbuf(gw.u64[1], mbuf, port, gw.u64[0] & 0xFFFFF, flags, @@ -212,7 +275,7 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev, ((uint64_t)port << 32); *(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr; cn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem, - ws->tstamp); + ws->tstamp, ws->lmt_base); } } @@ -290,7 +353,7 @@ uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port, uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events); -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_hot cn10k_sso_hws_deq_##name( \ void *port, struct rte_event *ev, uint64_t timeout_ticks); \ uint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \ diff --git a/drivers/event/cnxk/cn10k_worker_deq.c b/drivers/event/cnxk/cn10k_worker_deq.c index 36ec454..6083f69 100644 --- a/drivers/event/cnxk/cn10k_worker_deq.c +++ b/drivers/event/cnxk/cn10k_worker_deq.c @@ -6,7 +6,7 @@ #include "cnxk_eventdev.h" #include "cnxk_worker.h" -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_hot cn10k_sso_hws_deq_##name( \ void *port, struct rte_event *ev, uint64_t timeout_ticks) \ { \ diff --git a/drivers/event/cnxk/cn10k_worker_deq_burst.c b/drivers/event/cnxk/cn10k_worker_deq_burst.c index 29ecc55..8539d5d 100644 --- a/drivers/event/cnxk/cn10k_worker_deq_burst.c +++ b/drivers/event/cnxk/cn10k_worker_deq_burst.c @@ -6,7 +6,7 @@ #include "cnxk_eventdev.h" #include "cnxk_worker.h" -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_hot cn10k_sso_hws_deq_burst_##name( \ void *port, struct rte_event ev[], uint16_t nb_events, \ uint64_t timeout_ticks) \ diff --git a/drivers/event/cnxk/cn10k_worker_deq_ca.c b/drivers/event/cnxk/cn10k_worker_deq_ca.c index 508d30f..0d10fc8 100644 --- a/drivers/event/cnxk/cn10k_worker_deq_ca.c +++ b/drivers/event/cnxk/cn10k_worker_deq_ca.c @@ -6,7 +6,7 @@ #include "cnxk_eventdev.h" #include "cnxk_worker.h" -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_hot cn10k_sso_hws_deq_ca_##name( \ void *port, struct rte_event *ev, uint64_t timeout_ticks) \ { \ diff --git a/drivers/event/cnxk/cn10k_worker_deq_tmo.c b/drivers/event/cnxk/cn10k_worker_deq_tmo.c index c8524a2..537ae37 100644 --- a/drivers/event/cnxk/cn10k_worker_deq_tmo.c +++ b/drivers/event/cnxk/cn10k_worker_deq_tmo.c @@ -6,7 +6,7 @@ #include "cnxk_eventdev.h" #include "cnxk_worker.h" -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_hot cn10k_sso_hws_deq_tmo_##name( \ void *port, struct rte_event *ev, uint64_t timeout_ticks) \ { \ diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h index a888364..200cd93 100644 --- a/drivers/net/cnxk/cn10k_ethdev.h +++ b/drivers/net/cnxk/cn10k_ethdev.h @@ -81,4 +81,8 @@ void cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev); /* Security context setup */ void cn10k_eth_sec_ops_override(void); +#define LMT_OFF(lmt_addr, lmt_num, offset) \ + (void *)((uintptr_t)(lmt_addr) + \ + ((uint64_t)(lmt_num) << ROC_LMT_LINE_SIZE_LOG2) + (offset)) + #endif /* __CN10K_ETHDEV_H__ */ diff --git a/drivers/net/cnxk/cn10k_rx.c b/drivers/net/cnxk/cn10k_rx.c index 69e767a..d6af54b 100644 --- a/drivers/net/cnxk/cn10k_rx.c +++ b/drivers/net/cnxk/cn10k_rx.c @@ -5,7 +5,7 @@ #include "cn10k_ethdev.h" #include "cn10k_rx.h" -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_##name( \ void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \ { \ @@ -17,12 +17,13 @@ NIX_RX_FASTPATH_MODES static inline void pick_rx_func(struct rte_eth_dev *eth_dev, - const eth_rx_burst_t rx_burst[2][2][2][2][2][2]) + const eth_rx_burst_t rx_burst[2][2][2][2][2][2][2]) { struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); /* [VLAN] [TSP] [MARK] [CKSUM] [PTYPE] [RSS] */ eth_dev->rx_pkt_burst = rx_burst + [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F)] [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)] [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)] [!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)] @@ -38,33 +39,33 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev) { struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); - const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_##name, + const eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_##name, NIX_RX_FASTPATH_MODES #undef R }; - const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_mseg_##name, + const eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_mseg_##name, NIX_RX_FASTPATH_MODES #undef R }; - const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_##name, + const eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_##name, NIX_RX_FASTPATH_MODES #undef R }; - const eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2] = { -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ - [f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_mseg_##name, + const eth_rx_burst_t nix_eth_rx_vec_burst_mseg[2][2][2][2][2][2][2] = { +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ + [f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_recv_pkts_vec_mseg_##name, NIX_RX_FASTPATH_MODES #undef R @@ -73,7 +74,7 @@ cn10k_eth_set_rx_function(struct rte_eth_dev *eth_dev) /* Copy multi seg version with no offload for tear down sequence */ if (rte_eal_process_type() == RTE_PROC_PRIMARY) dev->rx_pkt_burst_no_offload = - nix_eth_rx_burst_mseg[0][0][0][0][0][0]; + nix_eth_rx_burst_mseg[0][0][0][0][0][0][0]; if (dev->scalar_ena) { if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index d27a231..fcc451a 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -65,6 +65,130 @@ nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off) return (struct rte_mbuf *)(buff - data_off); } +static __rte_always_inline void +nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff, + uintptr_t aura_handle) +{ + uint64_t pa; + + /* laddr is pointing to first pointer */ + laddr -= 8; + + /* Trigger free either on lmtline full or different aura handle */ + pa = roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_FREE0; + + /* Update aura handle */ + *(uint64_t *)laddr = (((uint64_t)(loff & 0x1) << 32) | + roc_npa_aura_handle_to_aura(aura_handle)); + + pa |= ((loff >> 1) << 4); + roc_lmt_submit_steorl(lmt_id, pa); +} + +static __rte_always_inline struct rte_mbuf * +nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, const uint64_t sa_base, uintptr_t laddr, + uint8_t *loff, struct rte_mbuf *mbuf, uint16_t data_off) +{ + const void *__p = (void *)((uintptr_t)mbuf + (uint16_t)data_off); + const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)__p; + struct cn10k_inb_priv_data *inb_priv; + struct rte_mbuf *inner; + uint32_t sa_idx; + void *inb_sa; + uint64_t w0; + + if (cq_w1 & BIT(11)) { + inner = (struct rte_mbuf *)(rte_be_to_cpu_64(hdr->wqe_ptr) - + sizeof(struct rte_mbuf)); + + /* Get SPI from CPT_PARSE_S's cookie(already swapped) */ + w0 = hdr->w0.u64; + sa_idx = w0 >> 32; + + inb_sa = roc_nix_inl_ot_ipsec_inb_sa(sa_base, sa_idx); + inb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa); + + /* Update dynamic field with userdata */ + *rte_security_dynfield(inner) = (uint64_t)inb_priv->userdata; + + /* Update l2 hdr length first */ + inner->pkt_len = (hdr->w2.il3_off - + sizeof(struct cpt_parse_hdr_s) - (w0 & 0x7)); + + /* Store meta in lmtline to free + * Assume all meta's from same aura. + */ + *(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf; + *loff = *loff + 1; + + return inner; + } + return mbuf; +} + +#if defined(RTE_ARCH_ARM64) + +static __rte_always_inline struct rte_mbuf * +nix_sec_meta_to_mbuf(uint64_t cq_w1, uintptr_t sa_base, uintptr_t laddr, + uint8_t *loff, struct rte_mbuf *mbuf, uint16_t data_off, + uint8x16_t *rx_desc_field1, uint64_t *ol_flags) +{ + const void *__p = (void *)((uintptr_t)mbuf + (uint16_t)data_off); + const struct cpt_parse_hdr_s *hdr = (const struct cpt_parse_hdr_s *)__p; + struct cn10k_inb_priv_data *inb_priv; + struct rte_mbuf *inner; + uint64_t *sg, res_w1; + uint32_t sa_idx; + void *inb_sa; + uint16_t len; + uint64_t w0; + + if (cq_w1 & BIT(11)) { + inner = (struct rte_mbuf *)(rte_be_to_cpu_64(hdr->wqe_ptr) - + sizeof(struct rte_mbuf)); + /* Get SPI from CPT_PARSE_S's cookie(already swapped) */ + w0 = hdr->w0.u64; + sa_idx = w0 >> 32; + + inb_sa = roc_nix_inl_ot_ipsec_inb_sa(sa_base, sa_idx); + inb_priv = roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(inb_sa); + + /* Update dynamic field with userdata */ + *rte_security_dynfield(inner) = (uint64_t)inb_priv->userdata; + + /* CPT result(struct cpt_cn10k_res_s) is at + * after first IOVA in meta + */ + sg = (uint64_t *)(inner + 1); + res_w1 = sg[10]; + + /* Clear checksum flags and update security flag */ + *ol_flags &= ~(PKT_RX_L4_CKSUM_MASK | PKT_RX_IP_CKSUM_MASK); + *ol_flags |= (((res_w1 & 0xFF) == CPT_COMP_WARN) ? + PKT_RX_SEC_OFFLOAD : + (PKT_RX_SEC_OFFLOAD | PKT_RX_SEC_OFFLOAD_FAILED)); + /* Calculate inner packet length */ + len = ((res_w1 >> 16) & 0xFFFF) + hdr->w2.il3_off - + sizeof(struct cpt_parse_hdr_s) - (w0 & 0x7); + /* Update pkt_len and data_len */ + *rx_desc_field1 = vsetq_lane_u16(len, *rx_desc_field1, 2); + *rx_desc_field1 = vsetq_lane_u16(len, *rx_desc_field1, 4); + + /* Store meta in lmtline to free + * Assume all meta's from same aura. + */ + *(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf; + *loff = *loff + 1; + + /* Return inner mbuf */ + return inner; + } + + /* Return same mbuf as it is not a decrypted pkt */ + return mbuf; +} +#endif + static __rte_always_inline uint32_t nix_ptype_get(const void *const lookup_mem, const uint64_t in) { @@ -177,8 +301,8 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag, { const union nix_rx_parse_u *rx = (const union nix_rx_parse_u *)((const uint64_t *)cq + 1); - const uint16_t len = rx->pkt_lenm1 + 1; const uint64_t w1 = *(const uint64_t *)rx; + uint16_t len = rx->pkt_lenm1 + 1; uint64_t ol_flags = 0; /* Mark mempool obj as "get" as it is alloc'ed by NIX */ @@ -194,8 +318,30 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag, ol_flags |= PKT_RX_RSS_HASH; } - if (flag & NIX_RX_OFFLOAD_CHECKSUM_F) - ol_flags |= nix_rx_olflags_get(lookup_mem, w1); + /* Process Security packets */ + if (flag & NIX_RX_OFFLOAD_SECURITY_F) { + if (w1 & BIT(11)) { + /* CPT result(struct cpt_cn10k_res_s) is at + * after first IOVA in meta + */ + const uint64_t *sg = (const uint64_t *)(mbuf + 1); + const uint64_t res_w1 = sg[10]; + const uint16_t uc_cc = res_w1 & 0xFF; + + /* Rlen */ + len = ((res_w1 >> 16) & 0xFFFF) + mbuf->pkt_len; + ol_flags |= ((uc_cc == CPT_COMP_WARN) ? + PKT_RX_SEC_OFFLOAD : + (PKT_RX_SEC_OFFLOAD | + PKT_RX_SEC_OFFLOAD_FAILED)); + } else { + if (flag & NIX_RX_OFFLOAD_CHECKSUM_F) + ol_flags |= nix_rx_olflags_get(lookup_mem, w1); + } + } else { + if (flag & NIX_RX_OFFLOAD_CHECKSUM_F) + ol_flags |= nix_rx_olflags_get(lookup_mem, w1); + } if (flag & NIX_RX_OFFLOAD_VLAN_STRIP_F) { if (rx->vtag0_gone) { @@ -263,13 +409,28 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, const uintptr_t desc = rxq->desc; const uint64_t wdata = rxq->wdata; const uint32_t qmask = rxq->qmask; + uint64_t lbase = rxq->lmt_base; uint16_t packets = 0, nb_pkts; + uint8_t loff = 0, lnum = 0; uint32_t head = rxq->head; struct nix_cqe_hdr_s *cq; struct rte_mbuf *mbuf; + uint64_t aura_handle; + uint64_t sa_base; + uint16_t lmt_id; + uint64_t laddr; nb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask); + if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + aura_handle = rxq->aura_handle; + sa_base = rxq->sa_base; + sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1); + ROC_LMT_BASE_ID_GET(lbase, lmt_id); + laddr = lbase; + laddr += 8; + } + while (packets < nb_pkts) { /* Prefetch N desc ahead */ rte_prefetch_non_temporal( @@ -278,6 +439,14 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, mbuf = nix_get_mbuf_from_cqe(cq, data_off); + /* Translate meta to mbuf */ + if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + const uint64_t cq_w1 = *((const uint64_t *)cq + 1); + + mbuf = nix_sec_meta_to_mbuf_sc(cq_w1, sa_base, laddr, + &loff, mbuf, data_off); + } + cn10k_nix_cqe_to_mbuf(cq, cq->tag, mbuf, lookup_mem, mbuf_init, flags); cnxk_nix_mbuf_to_tstamp(mbuf, rxq->tstamp, @@ -289,6 +458,20 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, roc_prefetch_store_keep(mbuf); head++; head &= qmask; + + if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + /* Flush when we don't have space for 4 meta */ + if ((15 - loff) < 1) { + nix_sec_flush_meta(laddr, lmt_id + lnum, loff, + aura_handle); + lnum++; + lnum &= BIT_ULL(ROC_LMT_LINES_PER_CORE_LOG2) - + 1; + /* First pointer starts at 8B offset */ + laddr = (uintptr_t)LMT_OFF(lbase, lnum, 8); + loff = 0; + } + } } rxq->head = head; @@ -297,6 +480,12 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts, /* Free all the CQs that we've processed */ plt_write64((wdata | nb_pkts), rxq->cq_door); + /* Free remaining meta buffers if any */ + if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) { + nix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle); + plt_io_wmb(); + } + return nb_pkts; } @@ -327,7 +516,8 @@ nix_qinq_update(const uint64_t w2, uint64_t ol_flags, struct rte_mbuf *mbuf) static __rte_always_inline uint16_t cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, const uint16_t flags, void *lookup_mem, - struct cnxk_timesync_info *tstamp) + struct cnxk_timesync_info *tstamp, + uintptr_t lmt_base) { struct cn10k_eth_rxq *rxq = args; const uint64_t mbuf_initializer = (flags & NIX_RX_VWQE_F) ? @@ -346,9 +536,13 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, uint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer); uint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer); struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3; + uint64_t aura_handle, lbase, laddr; + uint8_t loff = 0, lnum = 0; uint8x16_t f0, f1, f2, f3; + uint16_t lmt_id, d_off; uint16_t packets = 0; uint16_t pkts_left; + uintptr_t sa_base; uint32_t head; uintptr_t cq0; @@ -366,6 +560,38 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, RTE_SET_USED(head); } + if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + if (flags & NIX_RX_VWQE_F) { + uint16_t port; + + mbuf0 = (struct rte_mbuf *)((uintptr_t)mbufs[0] - + sizeof(struct rte_mbuf)); + /* Pick first mbuf's aura handle assuming all + * mbufs are from a vec and are from same RQ. + */ + aura_handle = mbuf0->pool->pool_id; + /* Calculate offset from mbuf to actual data area */ + d_off = ((uintptr_t)mbuf0->buf_addr - (uintptr_t)mbuf0); + d_off += (mbuf_initializer & 0xFFFF); + + /* Get SA Base from lookup tbl using port_id */ + port = mbuf_initializer >> 48; + sa_base = cnxk_nix_sa_base_get(port, lookup_mem); + + lbase = lmt_base; + } else { + aura_handle = rxq->aura_handle; + d_off = rxq->data_off; + sa_base = rxq->sa_base; + lbase = rxq->lmt_base; + } + sa_base &= ~(ROC_NIX_INL_SA_BASE_ALIGN - 1); + ROC_LMT_BASE_ID_GET(lbase, lmt_id); + lnum = 0; + laddr = lbase; + laddr += 8; + } + while (packets < pkts) { if (!(flags & NIX_RX_VWQE_F)) { /* Exit loop if head is about to wrap and become @@ -428,6 +654,14 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, f2 = vqtbl1q_u8(cq2_w8, shuf_msk); f3 = vqtbl1q_u8(cq3_w8, shuf_msk); + if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + /* Prefetch probable CPT parse header area */ + rte_prefetch_non_temporal(RTE_PTR_ADD(mbuf0, d_off)); + rte_prefetch_non_temporal(RTE_PTR_ADD(mbuf1, d_off)); + rte_prefetch_non_temporal(RTE_PTR_ADD(mbuf2, d_off)); + rte_prefetch_non_temporal(RTE_PTR_ADD(mbuf3, d_off)); + } + /* Load CQE word0 and word 1 */ const uint64_t cq0_w0 = *CQE_PTR_OFF(cq0, 0, 0, flags); const uint64_t cq0_w1 = *CQE_PTR_OFF(cq0, 0, 8, flags); @@ -474,6 +708,30 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, ol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1); } + /* Translate meta to mbuf */ + if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + /* Checksum ol_flags will be cleared if mbuf is meta */ + mbuf0 = nix_sec_meta_to_mbuf(cq0_w1, sa_base, laddr, + &loff, mbuf0, d_off, &f0, + &ol_flags0); + mbuf01 = vsetq_lane_u64((uint64_t)mbuf0, mbuf01, 0); + + mbuf1 = nix_sec_meta_to_mbuf(cq1_w1, sa_base, laddr, + &loff, mbuf1, d_off, &f1, + &ol_flags1); + mbuf01 = vsetq_lane_u64((uint64_t)mbuf1, mbuf01, 1); + + mbuf2 = nix_sec_meta_to_mbuf(cq2_w1, sa_base, laddr, + &loff, mbuf2, d_off, &f2, + &ol_flags2); + mbuf23 = vsetq_lane_u64((uint64_t)mbuf2, mbuf23, 0); + + mbuf3 = nix_sec_meta_to_mbuf(cq3_w1, sa_base, laddr, + &loff, mbuf3, d_off, &f3, + &ol_flags3); + mbuf23 = vsetq_lane_u64((uint64_t)mbuf3, mbuf23, 1); + } + if (flags & NIX_RX_OFFLOAD_VLAN_STRIP_F) { uint64_t cq0_w2 = *(uint64_t *)(cq0 + CQE_SZ(0) + 16); uint64_t cq1_w2 = *(uint64_t *)(cq0 + CQE_SZ(1) + 16); @@ -659,6 +917,26 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, head += NIX_DESCS_PER_LOOP; head &= qmask; } + + if (flags & NIX_RX_OFFLOAD_SECURITY_F) { + /* Flush when we don't have space for 4 meta */ + if ((15 - loff) < 4) { + nix_sec_flush_meta(laddr, lmt_id + lnum, loff, + aura_handle); + lnum++; + lnum &= BIT_ULL(ROC_LMT_LINES_PER_CORE_LOG2) - + 1; + /* First pointer starts at 8B offset */ + laddr = (uintptr_t)LMT_OFF(lbase, lnum, 8); + loff = 0; + } + } + } + + if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) { + nix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle); + if (flags & NIX_RX_VWQE_F) + plt_io_wmb(); } if (flags & NIX_RX_VWQE_F) @@ -681,16 +959,18 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, #else static inline uint16_t -cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts, - uint16_t pkts, const uint16_t flags, - void *lookup_mem, void *tstamp) +cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, + const uint16_t flags, void *lookup_mem, + struct cnxk_timesync_info *tstamp, + uintptr_t lmt_base) { - RTE_SET_USED(lookup_mem); - RTE_SET_USED(rx_queue); - RTE_SET_USED(rx_pkts); + RTE_SET_USED(args); + RTE_SET_USED(mbufs); RTE_SET_USED(pkts); RTE_SET_USED(flags); + RTE_SET_USED(lookup_mem); RTE_SET_USED(tstamp); + RTE_SET_USED(lmt_base); return 0; } @@ -704,98 +984,268 @@ cn10k_nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts, #define MARK_F NIX_RX_OFFLOAD_MARK_UPDATE_F #define TS_F NIX_RX_OFFLOAD_TSTAMP_F #define RX_VLAN_F NIX_RX_OFFLOAD_VLAN_STRIP_F +#define R_SEC_F NIX_RX_OFFLOAD_SECURITY_F -/* [RX_VLAN_F] [TS] [MARK] [CKSUM] [PTYPE] [RSS] */ +/* [R_SEC_F] [RX_VLAN_F] [TS] [MARK] [CKSUM] [PTYPE] [RSS] */ #define NIX_RX_FASTPATH_MODES \ -R(no_offload, 0, 0, 0, 0, 0, 0, NIX_RX_OFFLOAD_NONE) \ -R(rss, 0, 0, 0, 0, 0, 1, RSS_F) \ -R(ptype, 0, 0, 0, 0, 1, 0, PTYPE_F) \ -R(ptype_rss, 0, 0, 0, 0, 1, 1, PTYPE_F | RSS_F) \ -R(cksum, 0, 0, 0, 1, 0, 0, CKSUM_F) \ -R(cksum_rss, 0, 0, 0, 1, 0, 1, CKSUM_F | RSS_F) \ -R(cksum_ptype, 0, 0, 0, 1, 1, 0, CKSUM_F | PTYPE_F) \ -R(cksum_ptype_rss, 0, 0, 0, 1, 1, 1, CKSUM_F | PTYPE_F | RSS_F) \ -R(mark, 0, 0, 1, 0, 0, 0, MARK_F) \ -R(mark_rss, 0, 0, 1, 0, 0, 1, MARK_F | RSS_F) \ -R(mark_ptype, 0, 0, 1, 0, 1, 0, MARK_F | PTYPE_F) \ -R(mark_ptype_rss, 0, 0, 1, 0, 1, 1, MARK_F | PTYPE_F | RSS_F) \ -R(mark_cksum, 0, 0, 1, 1, 0, 0, MARK_F | CKSUM_F) \ -R(mark_cksum_rss, 0, 0, 1, 1, 0, 1, MARK_F | CKSUM_F | RSS_F) \ -R(mark_cksum_ptype, 0, 0, 1, 1, 1, 0, MARK_F | CKSUM_F | PTYPE_F) \ -R(mark_cksum_ptype_rss, 0, 0, 1, 1, 1, 1, \ - MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ -R(ts, 0, 1, 0, 0, 0, 0, TS_F) \ -R(ts_rss, 0, 1, 0, 0, 0, 1, TS_F | RSS_F) \ -R(ts_ptype, 0, 1, 0, 0, 1, 0, TS_F | PTYPE_F) \ -R(ts_ptype_rss, 0, 1, 0, 0, 1, 1, TS_F | PTYPE_F | RSS_F) \ -R(ts_cksum, 0, 1, 0, 1, 0, 0, TS_F | CKSUM_F) \ -R(ts_cksum_rss, 0, 1, 0, 1, 0, 1, TS_F | CKSUM_F | RSS_F) \ -R(ts_cksum_ptype, 0, 1, 0, 1, 1, 0, TS_F | CKSUM_F | PTYPE_F) \ -R(ts_cksum_ptype_rss, 0, 1, 0, 1, 1, 1, \ - TS_F | CKSUM_F | PTYPE_F | RSS_F) \ -R(ts_mark, 0, 1, 1, 0, 0, 0, TS_F | MARK_F) \ -R(ts_mark_rss, 0, 1, 1, 0, 0, 1, TS_F | MARK_F | RSS_F) \ -R(ts_mark_ptype, 0, 1, 1, 0, 1, 0, TS_F | MARK_F | PTYPE_F) \ -R(ts_mark_ptype_rss, 0, 1, 1, 0, 1, 1, \ - TS_F | MARK_F | PTYPE_F | RSS_F) \ -R(ts_mark_cksum, 0, 1, 1, 1, 0, 0, TS_F | MARK_F | CKSUM_F) \ -R(ts_mark_cksum_rss, 0, 1, 1, 1, 0, 1, \ - TS_F | MARK_F | CKSUM_F | RSS_F) \ -R(ts_mark_cksum_ptype, 0, 1, 1, 1, 1, 0, \ - TS_F | MARK_F | CKSUM_F | PTYPE_F) \ -R(ts_mark_cksum_ptype_rss, 0, 1, 1, 1, 1, 1, \ - TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ -R(vlan, 1, 0, 0, 0, 0, 0, RX_VLAN_F) \ -R(vlan_rss, 1, 0, 0, 0, 0, 1, RX_VLAN_F | RSS_F) \ -R(vlan_ptype, 1, 0, 0, 0, 1, 0, RX_VLAN_F | PTYPE_F) \ -R(vlan_ptype_rss, 1, 0, 0, 0, 1, 1, RX_VLAN_F | PTYPE_F | RSS_F) \ -R(vlan_cksum, 1, 0, 0, 1, 0, 0, RX_VLAN_F | CKSUM_F) \ -R(vlan_cksum_rss, 1, 0, 0, 1, 0, 1, RX_VLAN_F | CKSUM_F | RSS_F) \ -R(vlan_cksum_ptype, 1, 0, 0, 1, 1, 0, \ - RX_VLAN_F | CKSUM_F | PTYPE_F) \ -R(vlan_cksum_ptype_rss, 1, 0, 0, 1, 1, 1, \ - RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F) \ -R(vlan_mark, 1, 0, 1, 0, 0, 0, RX_VLAN_F | MARK_F) \ -R(vlan_mark_rss, 1, 0, 1, 0, 0, 1, RX_VLAN_F | MARK_F | RSS_F) \ -R(vlan_mark_ptype, 1, 0, 1, 0, 1, 0, RX_VLAN_F | MARK_F | PTYPE_F)\ -R(vlan_mark_ptype_rss, 1, 0, 1, 0, 1, 1, \ - RX_VLAN_F | MARK_F | PTYPE_F | RSS_F) \ -R(vlan_mark_cksum, 1, 0, 1, 1, 0, 0, RX_VLAN_F | MARK_F | CKSUM_F)\ -R(vlan_mark_cksum_rss, 1, 0, 1, 1, 0, 1, \ - RX_VLAN_F | MARK_F | CKSUM_F | RSS_F) \ -R(vlan_mark_cksum_ptype, 1, 0, 1, 1, 1, 0, \ - RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F) \ -R(vlan_mark_cksum_ptype_rss, 1, 0, 1, 1, 1, 1, \ - RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ -R(vlan_ts, 1, 1, 0, 0, 0, 0, RX_VLAN_F | TS_F) \ -R(vlan_ts_rss, 1, 1, 0, 0, 0, 1, RX_VLAN_F | TS_F | RSS_F) \ -R(vlan_ts_ptype, 1, 1, 0, 0, 1, 0, RX_VLAN_F | TS_F | PTYPE_F) \ -R(vlan_ts_ptype_rss, 1, 1, 0, 0, 1, 1, \ - RX_VLAN_F | TS_F | PTYPE_F | RSS_F) \ -R(vlan_ts_cksum, 1, 1, 0, 1, 0, 0, RX_VLAN_F | TS_F | CKSUM_F) \ -R(vlan_ts_cksum_rss, 1, 1, 0, 1, 0, 1, \ - RX_VLAN_F | TS_F | CKSUM_F | RSS_F) \ -R(vlan_ts_cksum_ptype, 1, 1, 0, 1, 1, 0, \ - RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F) \ -R(vlan_ts_cksum_ptype_rss, 1, 1, 0, 1, 1, 1, \ - RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \ -R(vlan_ts_mark, 1, 1, 1, 0, 0, 0, RX_VLAN_F | TS_F | MARK_F) \ -R(vlan_ts_mark_rss, 1, 1, 1, 0, 0, 1, \ - RX_VLAN_F | TS_F | MARK_F | RSS_F) \ -R(vlan_ts_mark_ptype, 1, 1, 1, 0, 1, 0, \ - RX_VLAN_F | TS_F | MARK_F | PTYPE_F) \ -R(vlan_ts_mark_ptype_rss, 1, 1, 1, 0, 1, 1, \ - RX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F) \ -R(vlan_ts_mark_cksum, 1, 1, 1, 1, 0, 0, \ - RX_VLAN_F | TS_F | MARK_F | CKSUM_F) \ -R(vlan_ts_mark_cksum_rss, 1, 1, 1, 1, 0, 1, \ - RX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F) \ -R(vlan_ts_mark_cksum_ptype, 1, 1, 1, 1, 1, 0, \ - RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \ -R(vlan_ts_mark_cksum_ptype_rss, 1, 1, 1, 1, 1, 1, \ - RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) +R(no_offload, 0, 0, 0, 0, 0, 0, 0, \ + NIX_RX_OFFLOAD_NONE) \ +R(rss, 0, 0, 0, 0, 0, 0, 1, \ + RSS_F) \ +R(ptype, 0, 0, 0, 0, 0, 1, 0, \ + PTYPE_F) \ +R(ptype_rss, 0, 0, 0, 0, 0, 1, 1, \ + PTYPE_F | RSS_F) \ +R(cksum, 0, 0, 0, 0, 1, 0, 0, \ + CKSUM_F) \ +R(cksum_rss, 0, 0, 0, 0, 1, 0, 1, \ + CKSUM_F | RSS_F) \ +R(cksum_ptype, 0, 0, 0, 0, 1, 1, 0, \ + CKSUM_F | PTYPE_F) \ +R(cksum_ptype_rss, 0, 0, 0, 0, 1, 1, 1, \ + CKSUM_F | PTYPE_F | RSS_F) \ +R(mark, 0, 0, 0, 1, 0, 0, 0, \ + MARK_F) \ +R(mark_rss, 0, 0, 0, 1, 0, 0, 1, \ + MARK_F | RSS_F) \ +R(mark_ptype, 0, 0, 0, 1, 0, 1, 0, \ + MARK_F | PTYPE_F) \ +R(mark_ptype_rss, 0, 0, 0, 1, 0, 1, 1, \ + MARK_F | PTYPE_F | RSS_F) \ +R(mark_cksum, 0, 0, 0, 1, 1, 0, 0, \ + MARK_F | CKSUM_F) \ +R(mark_cksum_rss, 0, 0, 0, 1, 1, 0, 1, \ + MARK_F | CKSUM_F | RSS_F) \ +R(mark_cksum_ptype, 0, 0, 0, 1, 1, 1, 0, \ + MARK_F | CKSUM_F | PTYPE_F) \ +R(mark_cksum_ptype_rss, 0, 0, 0, 1, 1, 1, 1, \ + MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(ts, 0, 0, 1, 0, 0, 0, 0, \ + TS_F) \ +R(ts_rss, 0, 0, 1, 0, 0, 0, 1, \ + TS_F | RSS_F) \ +R(ts_ptype, 0, 0, 1, 0, 0, 1, 0, \ + TS_F | PTYPE_F) \ +R(ts_ptype_rss, 0, 0, 1, 0, 0, 1, 1, \ + TS_F | PTYPE_F | RSS_F) \ +R(ts_cksum, 0, 0, 1, 0, 1, 0, 0, \ + TS_F | CKSUM_F) \ +R(ts_cksum_rss, 0, 0, 1, 0, 1, 0, 1, \ + TS_F | CKSUM_F | RSS_F) \ +R(ts_cksum_ptype, 0, 0, 1, 0, 1, 1, 0, \ + TS_F | CKSUM_F | PTYPE_F) \ +R(ts_cksum_ptype_rss, 0, 0, 1, 0, 1, 1, 1, \ + TS_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(ts_mark, 0, 0, 1, 1, 0, 0, 0, \ + TS_F | MARK_F) \ +R(ts_mark_rss, 0, 0, 1, 1, 0, 0, 1, \ + TS_F | MARK_F | RSS_F) \ +R(ts_mark_ptype, 0, 0, 1, 1, 0, 1, 0, \ + TS_F | MARK_F | PTYPE_F) \ +R(ts_mark_ptype_rss, 0, 0, 1, 1, 0, 1, 1, \ + TS_F | MARK_F | PTYPE_F | RSS_F) \ +R(ts_mark_cksum, 0, 0, 1, 1, 1, 0, 0, \ + TS_F | MARK_F | CKSUM_F) \ +R(ts_mark_cksum_rss, 0, 0, 1, 1, 1, 0, 1, \ + TS_F | MARK_F | CKSUM_F | RSS_F) \ +R(ts_mark_cksum_ptype, 0, 0, 1, 1, 1, 1, 0, \ + TS_F | MARK_F | CKSUM_F | PTYPE_F) \ +R(ts_mark_cksum_ptype_rss, 0, 0, 1, 1, 1, 1, 1, \ + TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(vlan, 0, 1, 0, 0, 0, 0, 0, \ + RX_VLAN_F) \ +R(vlan_rss, 0, 1, 0, 0, 0, 0, 1, \ + RX_VLAN_F | RSS_F) \ +R(vlan_ptype, 0, 1, 0, 0, 0, 1, 0, \ + RX_VLAN_F | PTYPE_F) \ +R(vlan_ptype_rss, 0, 1, 0, 0, 0, 1, 1, \ + RX_VLAN_F | PTYPE_F | RSS_F) \ +R(vlan_cksum, 0, 1, 0, 0, 1, 0, 0, \ + RX_VLAN_F | CKSUM_F) \ +R(vlan_cksum_rss, 0, 1, 0, 0, 1, 0, 1, \ + RX_VLAN_F | CKSUM_F | RSS_F) \ +R(vlan_cksum_ptype, 0, 1, 0, 0, 1, 1, 0, \ + RX_VLAN_F | CKSUM_F | PTYPE_F) \ +R(vlan_cksum_ptype_rss, 0, 1, 0, 0, 1, 1, 1, \ + RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(vlan_mark, 0, 1, 0, 1, 0, 0, 0, \ + RX_VLAN_F | MARK_F) \ +R(vlan_mark_rss, 0, 1, 0, 1, 0, 0, 1, \ + RX_VLAN_F | MARK_F | RSS_F) \ +R(vlan_mark_ptype, 0, 1, 0, 1, 0, 1, 0, \ + RX_VLAN_F | MARK_F | PTYPE_F) \ +R(vlan_mark_ptype_rss, 0, 1, 0, 1, 0, 1, 1, \ + RX_VLAN_F | MARK_F | PTYPE_F | RSS_F) \ +R(vlan_mark_cksum, 0, 1, 0, 1, 1, 0, 0, \ + RX_VLAN_F | MARK_F | CKSUM_F) \ +R(vlan_mark_cksum_rss, 0, 1, 0, 1, 1, 0, 1, \ + RX_VLAN_F | MARK_F | CKSUM_F | RSS_F) \ +R(vlan_mark_cksum_ptype, 0, 1, 0, 1, 1, 1, 0, \ + RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F) \ +R(vlan_mark_cksum_ptype_rss, 0, 1, 0, 1, 1, 1, 1, \ + RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(vlan_ts, 0, 1, 1, 0, 0, 0, 0, \ + RX_VLAN_F | TS_F) \ +R(vlan_ts_rss, 0, 1, 1, 0, 0, 0, 1, \ + RX_VLAN_F | TS_F | RSS_F) \ +R(vlan_ts_ptype, 0, 1, 1, 0, 0, 1, 0, \ + RX_VLAN_F | TS_F | PTYPE_F) \ +R(vlan_ts_ptype_rss, 0, 1, 1, 0, 0, 1, 1, \ + RX_VLAN_F | TS_F | PTYPE_F | RSS_F) \ +R(vlan_ts_cksum, 0, 1, 1, 0, 1, 0, 0, \ + RX_VLAN_F | TS_F | CKSUM_F) \ +R(vlan_ts_cksum_rss, 0, 1, 1, 0, 1, 0, 1, \ + RX_VLAN_F | TS_F | CKSUM_F | RSS_F) \ +R(vlan_ts_cksum_ptype, 0, 1, 1, 0, 1, 1, 0, \ + RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F) \ +R(vlan_ts_cksum_ptype_rss, 0, 1, 1, 0, 1, 1, 1, \ + RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(vlan_ts_mark, 0, 1, 1, 1, 0, 0, 0, \ + RX_VLAN_F | TS_F | MARK_F) \ +R(vlan_ts_mark_rss, 0, 1, 1, 1, 0, 0, 1, \ + RX_VLAN_F | TS_F | MARK_F | RSS_F) \ +R(vlan_ts_mark_ptype, 0, 1, 1, 1, 0, 1, 0, \ + RX_VLAN_F | TS_F | MARK_F | PTYPE_F) \ +R(vlan_ts_mark_ptype_rss, 0, 1, 1, 1, 0, 1, 1, \ + RX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F) \ +R(vlan_ts_mark_cksum, 0, 1, 1, 1, 1, 0, 0, \ + RX_VLAN_F | TS_F | MARK_F | CKSUM_F) \ +R(vlan_ts_mark_cksum_rss, 0, 1, 1, 1, 1, 0, 1, \ + RX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F) \ +R(vlan_ts_mark_cksum_ptype, 0, 1, 1, 1, 1, 1, 0, \ + RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \ +R(vlan_ts_mark_cksum_ptype_rss, 0, 1, 1, 1, 1, 1, 1, \ + RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(sec, 1, 0, 0, 0, 0, 0, 0, \ + R_SEC_F) \ +R(sec_rss, 1, 0, 0, 0, 0, 0, 1, \ + RSS_F) \ +R(sec_ptype, 1, 0, 0, 0, 0, 1, 0, \ + R_SEC_F | PTYPE_F) \ +R(sec_ptype_rss, 1, 0, 0, 0, 0, 1, 1, \ + R_SEC_F | PTYPE_F | RSS_F) \ +R(sec_cksum, 1, 0, 0, 0, 1, 0, 0, \ + R_SEC_F | CKSUM_F) \ +R(sec_cksum_rss, 1, 0, 0, 0, 1, 0, 1, \ + R_SEC_F | CKSUM_F | RSS_F) \ +R(sec_cksum_ptype, 1, 0, 0, 0, 1, 1, 0, \ + R_SEC_F | CKSUM_F | PTYPE_F) \ +R(sec_cksum_ptype_rss, 1, 0, 0, 0, 1, 1, 1, \ + R_SEC_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(sec_mark, 1, 0, 0, 1, 0, 0, 0, \ + R_SEC_F | MARK_F) \ +R(sec_mark_rss, 1, 0, 0, 1, 0, 0, 1, \ + R_SEC_F | MARK_F | RSS_F) \ +R(sec_mark_ptype, 1, 0, 0, 1, 0, 1, 0, \ + R_SEC_F | MARK_F | PTYPE_F) \ +R(sec_mark_ptype_rss, 1, 0, 0, 1, 0, 1, 1, \ + R_SEC_F | MARK_F | PTYPE_F | RSS_F) \ +R(sec_mark_cksum, 1, 0, 0, 1, 1, 0, 0, \ + R_SEC_F | MARK_F | CKSUM_F) \ +R(sec_mark_cksum_rss, 1, 0, 0, 1, 1, 0, 1, \ + R_SEC_F | MARK_F | CKSUM_F | RSS_F) \ +R(sec_mark_cksum_ptype, 1, 0, 0, 1, 1, 1, 0, \ + R_SEC_F | MARK_F | CKSUM_F | PTYPE_F) \ +R(sec_mark_cksum_ptype_rss, 1, 0, 0, 1, 1, 1, 1, \ + R_SEC_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(sec_ts, 1, 0, 1, 0, 0, 0, 0, \ + R_SEC_F | TS_F) \ +R(sec_ts_rss, 1, 0, 1, 0, 0, 0, 1, \ + R_SEC_F | TS_F | RSS_F) \ +R(sec_ts_ptype, 1, 0, 1, 0, 0, 1, 0, \ + R_SEC_F | TS_F | PTYPE_F) \ +R(sec_ts_ptype_rss, 1, 0, 1, 0, 0, 1, 1, \ + R_SEC_F | TS_F | PTYPE_F | RSS_F) \ +R(sec_ts_cksum, 1, 0, 1, 0, 1, 0, 0, \ + R_SEC_F | TS_F | CKSUM_F) \ +R(sec_ts_cksum_rss, 1, 0, 1, 0, 1, 0, 1, \ + R_SEC_F | TS_F | CKSUM_F | RSS_F) \ +R(sec_ts_cksum_ptype, 1, 0, 1, 0, 1, 1, 0, \ + R_SEC_F | TS_F | CKSUM_F | PTYPE_F) \ +R(sec_ts_cksum_ptype_rss, 1, 0, 1, 0, 1, 1, 1, \ + R_SEC_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(sec_ts_mark, 1, 0, 1, 1, 0, 0, 0, \ + R_SEC_F | TS_F | MARK_F) \ +R(sec_ts_mark_rss, 1, 0, 1, 1, 0, 0, 1, \ + R_SEC_F | TS_F | MARK_F | RSS_F) \ +R(sec_ts_mark_ptype, 1, 0, 1, 1, 0, 1, 0, \ + R_SEC_F | TS_F | MARK_F | PTYPE_F) \ +R(sec_ts_mark_ptype_rss, 1, 0, 1, 1, 0, 1, 1, \ + R_SEC_F | TS_F | MARK_F | PTYPE_F | RSS_F) \ +R(sec_ts_mark_cksum, 1, 0, 1, 1, 1, 0, 0, \ + R_SEC_F | TS_F | MARK_F | CKSUM_F) \ +R(sec_ts_mark_cksum_rss, 1, 0, 1, 1, 1, 0, 1, \ + R_SEC_F | TS_F | MARK_F | CKSUM_F | RSS_F) \ +R(sec_ts_mark_cksum_ptype, 1, 0, 1, 1, 1, 1, 0, \ + R_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \ +R(sec_ts_mark_cksum_ptype_rss, 1, 0, 1, 1, 1, 1, 1, \ + R_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(sec_vlan, 1, 1, 0, 0, 0, 0, 0, \ + R_SEC_F | RX_VLAN_F) \ +R(sec_vlan_rss, 1, 1, 0, 0, 0, 0, 1, \ + R_SEC_F | RX_VLAN_F | RSS_F) \ +R(sec_vlan_ptype, 1, 1, 0, 0, 0, 1, 0, \ + R_SEC_F | RX_VLAN_F | PTYPE_F) \ +R(sec_vlan_ptype_rss, 1, 1, 0, 0, 0, 1, 1, \ + R_SEC_F | RX_VLAN_F | PTYPE_F | RSS_F) \ +R(sec_vlan_cksum, 1, 1, 0, 0, 1, 0, 0, \ + R_SEC_F | RX_VLAN_F | CKSUM_F) \ +R(sec_vlan_cksum_rss, 1, 1, 0, 0, 1, 0, 1, \ + R_SEC_F | RX_VLAN_F | CKSUM_F | RSS_F) \ +R(sec_vlan_cksum_ptype, 1, 1, 0, 0, 1, 1, 0, \ + R_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F) \ +R(sec_vlan_cksum_ptype_rss, 1, 1, 0, 0, 1, 1, 1, \ + R_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(sec_vlan_mark, 1, 1, 0, 1, 0, 0, 0, \ + R_SEC_F | RX_VLAN_F | MARK_F) \ +R(sec_vlan_mark_rss, 1, 1, 0, 1, 0, 0, 1, \ + R_SEC_F | RX_VLAN_F | MARK_F | RSS_F) \ +R(sec_vlan_mark_ptype, 1, 1, 0, 1, 0, 1, 0, \ + R_SEC_F | RX_VLAN_F | MARK_F | PTYPE_F) \ +R(sec_vlan_mark_ptype_rss, 1, 1, 0, 1, 0, 1, 1, \ + R_SEC_F | RX_VLAN_F | MARK_F | PTYPE_F | RSS_F) \ +R(sec_vlan_mark_cksum, 1, 1, 0, 1, 1, 0, 0, \ + R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F) \ +R(sec_vlan_mark_cksum_rss, 1, 1, 0, 1, 1, 0, 1, \ + R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | RSS_F) \ +R(sec_vlan_mark_cksum_ptype, 1, 1, 0, 1, 1, 1, 0, \ + R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F) \ +R(sec_vlan_mark_cksum_ptype_rss, 1, 1, 0, 1, 1, 1, 1, \ + R_SEC_F | RX_VLAN_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(sec_vlan_ts, 1, 1, 1, 0, 0, 0, 0, \ + R_SEC_F | RX_VLAN_F | TS_F) \ +R(sec_vlan_ts_rss, 1, 1, 1, 0, 0, 0, 1, \ + R_SEC_F | RX_VLAN_F | TS_F | RSS_F) \ +R(sec_vlan_ts_ptype, 1, 1, 1, 0, 0, 1, 0, \ + R_SEC_F | RX_VLAN_F | TS_F | PTYPE_F) \ +R(sec_vlan_ts_ptype_rss, 1, 1, 1, 0, 0, 1, 1, \ + R_SEC_F | RX_VLAN_F | TS_F | PTYPE_F | RSS_F) \ +R(sec_vlan_ts_cksum, 1, 1, 1, 0, 1, 0, 0, \ + R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F) \ +R(sec_vlan_ts_cksum_rss, 1, 1, 1, 0, 1, 0, 1, \ + R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | RSS_F) \ +R(sec_vlan_ts_cksum_ptype, 1, 1, 1, 0, 1, 1, 0, \ + R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F) \ +R(sec_vlan_ts_cksum_ptype_rss, 1, 1, 1, 0, 1, 1, 1, \ + R_SEC_F | RX_VLAN_F | TS_F | CKSUM_F | PTYPE_F | RSS_F) \ +R(sec_vlan_ts_mark, 1, 1, 1, 1, 0, 0, 0, \ + R_SEC_F | RX_VLAN_F | TS_F | MARK_F) \ +R(sec_vlan_ts_mark_rss, 1, 1, 1, 1, 0, 0, 1, \ + R_SEC_F | RX_VLAN_F | TS_F | MARK_F | RSS_F) \ +R(sec_vlan_ts_mark_ptype, 1, 1, 1, 1, 0, 1, 0, \ + R_SEC_F | RX_VLAN_F | TS_F | MARK_F | PTYPE_F) \ +R(sec_vlan_ts_mark_ptype_rss, 1, 1, 1, 1, 0, 1, 1, \ + R_SEC_F | RX_VLAN_F | TS_F | MARK_F | PTYPE_F | RSS_F) \ +R(sec_vlan_ts_mark_cksum, 1, 1, 1, 1, 1, 0, 0, \ + R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F) \ +R(sec_vlan_ts_mark_cksum_rss, 1, 1, 1, 1, 1, 0, 1, \ + R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | RSS_F) \ +R(sec_vlan_ts_mark_cksum_ptype, 1, 1, 1, 1, 1, 1, 0, \ + R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F) \ +R(sec_vlan_ts_mark_cksum_ptype_rss, 1, 1, 1, 1, 1, 1, 1, \ + R_SEC_F | RX_VLAN_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_##name( \ void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts); \ \ diff --git a/drivers/net/cnxk/cn10k_rx_mseg.c b/drivers/net/cnxk/cn10k_rx_mseg.c index 3340771..e7c2321 100644 --- a/drivers/net/cnxk/cn10k_rx_mseg.c +++ b/drivers/net/cnxk/cn10k_rx_mseg.c @@ -5,7 +5,7 @@ #include "cn10k_ethdev.h" #include "cn10k_rx.h" -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_mseg_##name( \ void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \ { \ diff --git a/drivers/net/cnxk/cn10k_rx_vec.c b/drivers/net/cnxk/cn10k_rx_vec.c index 166735a..0ccc4df 100644 --- a/drivers/net/cnxk/cn10k_rx_vec.c +++ b/drivers/net/cnxk/cn10k_rx_vec.c @@ -5,14 +5,14 @@ #include "cn10k_ethdev.h" #include "cn10k_rx.h" -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_noinline __rte_hot \ cn10k_nix_recv_pkts_vec_##name(void *rx_queue, \ struct rte_mbuf **rx_pkts, \ uint16_t pkts) \ { \ return cn10k_nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, \ - (flags), NULL, NULL); \ + (flags), NULL, NULL, 0); \ } NIX_RX_FASTPATH_MODES diff --git a/drivers/net/cnxk/cn10k_rx_vec_mseg.c b/drivers/net/cnxk/cn10k_rx_vec_mseg.c index 1f44ddd..38e0ec3 100644 --- a/drivers/net/cnxk/cn10k_rx_vec_mseg.c +++ b/drivers/net/cnxk/cn10k_rx_vec_mseg.c @@ -5,13 +5,13 @@ #include "cn10k_ethdev.h" #include "cn10k_rx.h" -#define R(name, f5, f4, f3, f2, f1, f0, flags) \ +#define R(name, f6, f5, f4, f3, f2, f1, f0, flags) \ uint16_t __rte_noinline __rte_hot cn10k_nix_recv_pkts_vec_mseg_##name( \ void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts) \ { \ return cn10k_nix_recv_pkts_vector( \ rx_queue, rx_pkts, pkts, (flags) | NIX_RX_MULTI_SEG_F, \ - NULL, NULL); \ + NULL, NULL, 0); \ } NIX_RX_FASTPATH_MODES diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 8577a7b..c81a612 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -51,9 +51,6 @@ #define NIX_NB_SEGS_TO_SEGDW(x) ((NIX_SEGDW_MAGIC >> ((x) << 2)) & 0xF) -#define LMT_OFF(lmt_addr, lmt_num, offset) \ - (void *)((lmt_addr) + ((lmt_num) << ROC_LMT_LINE_SIZE_LOG2) + (offset)) - /* Function to determine no of tx subdesc required in case ext * sub desc is enabled. */