From patchwork Thu Sep 2 02:14:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 97733 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AF54EA0C4C; Thu, 2 Sep 2021 04:17:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BF8FD410EA; Thu, 2 Sep 2021 04:17:11 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C342D410EA for ; Thu, 2 Sep 2021 04:17:09 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 181K5SYj027320 for ; Wed, 1 Sep 2021 19:17:09 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=eHZsMW8bkw1WaiP4DG9B9rVEcb6KEgERNiS8rMahLsY=; b=KO5aX+32/cjl7I1GEAapNr5DReJjgBJTdIEwDS8ll6addgamcUn1uNLPVz8duMxxj6dZ xALIdiPSfSuLTjKEApbpAQkv8gQB53FUZVHuUlkwMcyeuOA59hoEkJfaTpTM0tcCN6MC hsTGuMGiCe4idojgq9mBcuSbcUr1Qu8xFcMgNn0OPQLvq+hCkMLXemDht/VPlBJX5yZe dc7GPwQCAHI7iECmF7eFYvegpZ7RWTvLxsSHC4ydCiFRcrbHzAggo4R+CWYwRGInTnZX fFHhIM2GdNskPne0oSgg8TA2+c9r6MhzZK6mjnrC3vU15Do91DTsld5CGwRBH35BKWzj GA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 3atg8a91h4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 01 Sep 2021 19:17:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 1 Sep 2021 19:17:07 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Wed, 1 Sep 2021 19:17:07 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 4DE4B3F704D; Wed, 1 Sep 2021 19:17:05 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Date: Thu, 2 Sep 2021 07:44:46 +0530 Message-ID: <20210902021505.17607-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210902021505.17607-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 10pWd-VwpXagIGlrmlv9dmU1R3hKo9u- X-Proofpoint-ORIG-GUID: 10pWd-VwpXagIGlrmlv9dmU1R3hKo9u- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 08/27] common/cnxk: dump cpt lf registers on error intr X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Dump CPT LF registers on error interrupt. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_cpt.c | 5 ++++- drivers/common/cnxk/roc_cpt_debug.c | 32 ++++++++++++++++++++++++++++++-- drivers/common/cnxk/roc_cpt_priv.h | 1 + 3 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 3222b3e..f08b5d0 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -51,6 +51,9 @@ cpt_lf_misc_irq(void *param) plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf); + /* Dump lf registers */ + cpt_lf_print(lf); + /* Clear interrupt */ plt_write64(intr, lf->rbase + CPT_LF_MISC_INT); } @@ -203,7 +206,7 @@ cpt_lf_dump(struct roc_cpt_lf *lf) plt_cpt_dbg("CPT LF REG:"); plt_cpt_dbg("LF_CTL[0x%016llx]: 0x%016" PRIx64, CPT_LF_CTL, plt_read64(lf->rbase + CPT_LF_CTL)); - plt_cpt_dbg("Q_SIZE[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG, + plt_cpt_dbg("LF_INPROG[0x%016llx]: 0x%016" PRIx64, CPT_LF_INPROG, plt_read64(lf->rbase + CPT_LF_INPROG)); plt_cpt_dbg("Q_BASE[0x%016llx]: 0x%016" PRIx64, CPT_LF_Q_BASE, diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c index a6c9004..847d969 100644 --- a/drivers/common/cnxk/roc_cpt_debug.c +++ b/drivers/common/cnxk/roc_cpt_debug.c @@ -157,11 +157,40 @@ roc_cpt_afs_print(struct roc_cpt *roc_cpt) return 0; } -static void +void cpt_lf_print(struct roc_cpt_lf *lf) { uint64_t reg_val; + reg_val = plt_read64(lf->rbase + CPT_LF_Q_BASE); + plt_print(" CPT_LF_Q_BASE:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_Q_SIZE); + plt_print(" CPT_LF_Q_SIZE:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_Q_INST_PTR); + plt_print(" CPT_LF_Q_INST_PTR:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR); + plt_print(" CPT_LF_Q_GRP_PTR:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_CTL); + plt_print(" CPT_LF_CTL:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT_ENA_W1S); + plt_print(" CPT_LF_MISC_INT_ENA_W1S:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_MISC_INT); + plt_print(" CPT_LF_MISC_INT:\t%016lx", reg_val); + + reg_val = plt_read64(lf->rbase + CPT_LF_INPROG); + plt_print(" CPT_LF_INPROG:\t%016lx", reg_val); + + if (roc_model_is_cn9k()) + return; + + plt_print("Count registers for CPT LF%d:", lf->lf_id); + reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_BYTE_CNT); plt_print(" Encrypted byte count:\t%" PRIu64, reg_val); @@ -190,7 +219,6 @@ roc_cpt_lfs_print(struct roc_cpt *roc_cpt) if (lf == NULL) continue; - plt_print("Count registers for CPT LF%d:", lf_id); cpt_lf_print(lf); } diff --git a/drivers/common/cnxk/roc_cpt_priv.h b/drivers/common/cnxk/roc_cpt_priv.h index 21911e5..61dec9a 100644 --- a/drivers/common/cnxk/roc_cpt_priv.h +++ b/drivers/common/cnxk/roc_cpt_priv.h @@ -31,5 +31,6 @@ int cpt_lf_outb_cfg(struct dev *dev, uint16_t sso_pf_func, uint16_t nix_pf_func, uint8_t lf_id, bool ena); int cpt_get_msix_offset(struct dev *dev, struct msix_offset_rsp **msix_rsp); uint64_t cpt_get_blkaddr(struct dev *dev); +void cpt_lf_print(struct roc_cpt_lf *lf); #endif /* _ROC_CPT_PRIV_H_ */