From patchwork Thu Sep 30 17:00:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 100146 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3EF34A0C43; Thu, 30 Sep 2021 19:03:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6ECC641145; Thu, 30 Sep 2021 19:02:44 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id ED7F7410FE for ; Thu, 30 Sep 2021 19:02:03 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 18UF7qA1018525 for ; Thu, 30 Sep 2021 10:02:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=wY5bHeDxAKzYDuexIQ+dKVRsJgqTjhGHmZ48qumknXY=; b=ISEmMiWiMWW8u82IBW9g4G9FWtDq0+zFZGDz/EodWGdIXOrd+hU564SNZUrgdjhX/O/a jDNoZ1FrwU7vDZ5Q+G8mkLS/qMQ5boDA6Z48OPLC/gxu38pBJYPLWEtiVpiaH3Z77xsm IGfdFinBxyioYyvC290jm5+nKoRc2QPUoeGLdzUHwZgZf++UJq3Xna51MZosc0eJfjso rqbxQqlbj52Gjt3FQ0vJcLGROI9B2faMNFq4H6k66OHlCKqVna5fa0yGWDS9m3zeTz3m brZDugsAsQTrpkPZmYvlUhGfm6vUF7wvb3I6+JbkvGCHW5b+RtanA6t0kpft7eJ3ImGb Dw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bd3g3b9g4-14 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 30 Sep 2021 10:02:02 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep 2021 10:01:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 30 Sep 2021 10:01:48 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 39ADE3F706D; Thu, 30 Sep 2021 10:01:45 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Date: Thu, 30 Sep 2021 22:30:55 +0530 Message-ID: <20210930170113.29030-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210930170113.29030-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> <20210930170113.29030-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: S8CZaBG0z7irRf5xXgIDfgndDC6pzAFK X-Proofpoint-ORIG-GUID: S8CZaBG0z7irRf5xXgIDfgndDC6pzAFK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-30_06,2021-09-30_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH v2 10/28] common/cnxk: align CPT LF enable/disable sequence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For CPT LF IQ enable, set CPT_LF_CTL[ENA] before setting CPT_LF_INPROG[EENA] to true. For CPT LF IQ disable, align sequence to that of HRM. Also this patch aligns space for instructions in CPT LF to ROC_ALIGN to make complete memory cache aligned and has other minor fixes/additions. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/hw/cpt.h | 11 +++++++++++ drivers/common/cnxk/roc_cpt.c | 42 ++++++++++++++++++++++++++++++++++-------- drivers/common/cnxk/roc_cpt.h | 8 ++++++++ 3 files changed, 53 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h index 975139f..4d9df59 100644 --- a/drivers/common/cnxk/hw/cpt.h +++ b/drivers/common/cnxk/hw/cpt.h @@ -124,6 +124,17 @@ union cpt_lf_misc_int { } s; }; +union cpt_lf_q_grp_ptr { + uint64_t u; + struct { + uint64_t dq_ptr : 15; + uint64_t reserved_31_15 : 17; + uint64_t nq_ptr : 15; + uint64_t reserved_47_62 : 16; + uint64_t xq_xor : 1; + } s; +}; + union cpt_inst_w4 { uint64_t u64; struct { diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 6ddbaa2..68fdb27 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -437,8 +437,10 @@ cpt_lf_iq_mem_calc(uint32_t nb_desc) len += CPT_IQ_FC_LEN; /* For instruction queues */ - len += CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_NB_DESC_MULTIPLIER * - sizeof(struct cpt_inst_s); + len += PLT_ALIGN(CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * + CPT_IQ_NB_DESC_MULTIPLIER * + sizeof(struct cpt_inst_s), + ROC_ALIGN); return len; } @@ -550,6 +552,7 @@ cpt_lf_init(struct roc_cpt_lf *lf) iq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN); if (iq_mem == NULL) return -ENOMEM; + plt_atomic_thread_fence(__ATOMIC_ACQ_REL); blkaddr = cpt_get_blkaddr(dev); lf->rbase = dev->bar2 + ((blkaddr << 20) | (lf->lf_id << 12)); @@ -634,7 +637,7 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt) } /* Reserve 1 CPT LF for inline inbound */ - nb_lf_avail = PLT_MIN(nb_lf_avail, ROC_CPT_MAX_LFS - 1); + nb_lf_avail = PLT_MIN(nb_lf_avail, (uint16_t)(ROC_CPT_MAX_LFS - 1)); roc_cpt->nb_lf_avail = nb_lf_avail; @@ -770,8 +773,10 @@ void roc_cpt_iq_disable(struct roc_cpt_lf *lf) { union cpt_lf_ctl lf_ctl = {.u = 0x0}; + union cpt_lf_q_grp_ptr grp_ptr; union cpt_lf_inprog lf_inprog; int timeout = 20; + int cnt; /* Disable instructions enqueuing */ plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL); @@ -795,6 +800,27 @@ roc_cpt_iq_disable(struct roc_cpt_lf *lf) */ lf_inprog.s.eena = 0x0; plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG); + + /* Wait for instruction queue to become empty */ + cnt = 0; + do { + lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG); + if (lf_inprog.s.grb_partial) + cnt = 0; + else + cnt++; + grp_ptr.u = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR); + } while ((cnt < 10) && (grp_ptr.s.nq_ptr != grp_ptr.s.dq_ptr)); + + cnt = 0; + do { + lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG); + if ((lf_inprog.s.inflight == 0) && (lf_inprog.s.gwb_cnt < 40) && + ((lf_inprog.s.grb_cnt == 0) || (lf_inprog.s.grb_cnt == 40))) + cnt++; + else + cnt = 0; + } while (cnt < 10); } void @@ -806,11 +832,6 @@ roc_cpt_iq_enable(struct roc_cpt_lf *lf) /* Disable command queue */ roc_cpt_iq_disable(lf); - /* Enable command queue execution */ - lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG); - lf_inprog.s.eena = 1; - plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG); - /* Enable instruction queue enqueuing */ lf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL); lf_ctl.s.ena = 1; @@ -819,6 +840,11 @@ roc_cpt_iq_enable(struct roc_cpt_lf *lf) lf_ctl.s.fc_hyst_bits = lf->fc_hyst_bits; plt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL); + /* Enable command queue execution */ + lf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG); + lf_inprog.s.eena = 1; + plt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG); + cpt_lf_dump(lf); } diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index c80a8e0..06277d1 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -76,6 +76,14 @@ #define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20 #define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40 +#define ROC_CPT_CCM_AAD_DATA 1 +#define ROC_CPT_CCM_MSG_LEN 4 +#define ROC_CPT_CCM_ICV_LEN 16 +#define ROC_CPT_CCM_FLAGS \ + ((ROC_CPT_CCM_AAD_DATA << 6) | \ + (((ROC_CPT_CCM_ICV_LEN - 2) / 2) << 3) | (ROC_CPT_CCM_MSG_LEN - 1)) +#define ROC_CPT_CCM_SALT_LEN 3 + struct roc_cpt_lmtline { uint64_t io_addr; uint64_t *fc_addr;