From patchwork Fri Oct 1 13:40:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 100270 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6AAECA0032; Fri, 1 Oct 2021 15:43:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 789E941214; Fri, 1 Oct 2021 15:41:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2337041231 for ; Fri, 1 Oct 2021 15:41:39 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 191AGLCE010080 for ; Fri, 1 Oct 2021 06:41:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=Y9axsa72oHh7Lba5wp/fxIgX27st17kXuGYYhoJma8A=; b=X2UkUc5mG/ryG1QapBIIbJvUl6aMaVIxVl4+halkdkybkoDxJWqFwZfzIUVzwjHk/Qoq tQFfDCNwLEZXdHt3Uf4ccKQfi8nXyTtKeLxk1tX9s2iKu7jE4kTUjXgkVjOa+38Zxs95 oJQLGtrTXD+THL7jsK8tZ9XJTfXwE4aznxcKPMGGDCWTo1FnHuLClDp1Upnqx4godCpz QyG2bJtylzs/kF3jj0KICblgo3i7iQMdx6jRskuN7KrXzOTnmNZclvGon4EYFgbKEf4W FUQ7EalvbUx0YozPtm4vG1U53+euCYNwPHQXP0c9G1vH7ztb6wvPn8MYqSiodwHFajh8 Gg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3bdrxmhxe3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 01 Oct 2021 06:41:38 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 1 Oct 2021 06:41:36 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 1 Oct 2021 06:41:36 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0D24E3F7041; Fri, 1 Oct 2021 06:41:33 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Srujana Challa Date: Fri, 1 Oct 2021 19:10:18 +0530 Message-ID: <20211001134022.22700-25-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211001134022.22700-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> <20211001134022.22700-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: UAsH61NL4xwK55o_cRZ3ei9fDdmnFK1Z X-Proofpoint-ORIG-GUID: UAsH61NL4xwK55o_cRZ3ei9fDdmnFK1Z X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-01_02,2021-10-01_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 24/28] net/cnxk: update ethertype for mixed IPsec tunnel versions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Srujana Challa Adds support to update ethertype for mixed IPsec tunnel versions. And also sets et_overwr for inbound IPsec. Signed-off-by: Srujana Challa --- drivers/common/cnxk/cnxk_security.c | 1 + drivers/net/cnxk/cn10k_ethdev.h | 3 ++- drivers/net/cnxk/cn10k_ethdev_sec.c | 2 ++ drivers/net/cnxk/cn10k_tx.h | 19 +++++++++++++++++++ 4 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c index c117fa7..0039a9d 100644 --- a/drivers/common/cnxk/cnxk_security.c +++ b/drivers/common/cnxk/cnxk_security.c @@ -344,6 +344,7 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa, /* There are two words of CPT_CTX_HW_S for ucode to skip */ sa->w0.s.ctx_hdr_size = 1; sa->w0.s.aop_valid = 1; + sa->w0.s.et_ovrwr = 1; rte_wmb(); diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h index 200cd93..c2a46ad 100644 --- a/drivers/net/cnxk/cn10k_ethdev.h +++ b/drivers/net/cnxk/cn10k_ethdev.h @@ -64,7 +64,8 @@ struct cn10k_sec_sess_priv { struct { uint32_t sa_idx; uint8_t inb_sa : 1; - uint8_t rsvd1 : 2; + uint8_t outer_ip_ver : 1; + uint8_t mode : 1; uint8_t roundup_byte : 5; uint8_t roundup_len; uint16_t partial_len; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index dae5ea7..c66730a 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -341,6 +341,8 @@ cn10k_eth_sec_session_create(void *device, sess_priv.roundup_byte = rlens->roundup_byte; sess_priv.roundup_len = rlens->roundup_len; sess_priv.partial_len = rlens->partial_len; + sess_priv.mode = outb_sa->w2.s.ipsec_mode; + sess_priv.outer_ip_ver = outb_sa->w2.s.outer_ip_ver; /* Pointer from eth_sec -> outb_sa */ eth_sec->sa = outb_sa; diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 52bb71d..ad84464 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -302,6 +302,16 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1); dptr += l2_len; + + if (sess_priv.mode == ROC_IE_SA_MODE_TUNNEL) { + if (sess_priv.outer_ip_ver == ROC_IE_SA_IP_VERSION_4) + *((uint16_t *)(dptr - 2)) = + rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4); + else + *((uint16_t *)(dptr - 2)) = + rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6); + } + ucode_cmd[1] = dptr; ucode_cmd[2] = dptr; @@ -396,6 +406,15 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1); dptr += l2_len; + + if (sess_priv.mode == ROC_IE_SA_MODE_TUNNEL) { + if (sess_priv.outer_ip_ver == ROC_IE_SA_IP_VERSION_4) + *((uint16_t *)(dptr - 2)) = + rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4); + else + *((uint16_t *)(dptr - 2)) = + rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6); + } ucode_cmd[1] = dptr; ucode_cmd[2] = dptr;