From patchwork Fri Oct 1 13:40:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 100274 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 893C2A0032; Fri, 1 Oct 2021 15:43:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EDF92411F9; Fri, 1 Oct 2021 15:41:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 383564123F; Fri, 1 Oct 2021 15:41:50 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 191AGLCF010080; Fri, 1 Oct 2021 06:41:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=gT38LFdngK2JRLGl03sk/gJFk1zzOXXmylCCuP8FdU4=; b=AzlSb+yDcbEAkbIku3aChPYjm3nCRJ4AqWqZkmIbxKh5/T3kCqaCof3l2mASqfu7+whE 95a3CwnHr3wVbGhuThs8Z2RvdlADOK5ME5g1OXjR+6hYPQB22jsbCWVbj+UG+r3XMZou M/TB0a4u+btsJTBFa7YS4dwoGoZv7y/sGjA382gO3kc/KLTDXkRPI1j235j0IEPH5lvw Dk53fnDlOJ8HDtwS12C8SlE4CNdMNSLa5LgcUiddlbpbaWTdaGmOqhL91bNELwEgST8g PjpjMK6Lqk5aL+thh//62jSCIiM7ifJk7LWWKRbSgXJI7/eIx6vqhpCEtRuoByZRtx6k dg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bdrxmhxf0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 01 Oct 2021 06:41:49 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 1 Oct 2021 06:41:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 1 Oct 2021 06:41:47 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 67B463F7043; Fri, 1 Oct 2021 06:41:45 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Date: Fri, 1 Oct 2021 19:10:22 +0530 Message-ID: <20211001134022.22700-29-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211001134022.22700-1-ndabilpuram@marvell.com> References: <20210902021505.17607-1-ndabilpuram@marvell.com> <20211001134022.22700-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: JpaauCEvdYhgFhRWVnfl2dfZTGNfJ4Tp X-Proofpoint-ORIG-GUID: JpaauCEvdYhgFhRWVnfl2dfZTGNfJ4Tp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-01_02,2021-10-01_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH v3 28/28] net/cnxk: reflect globally enabled offloads in queue conf X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reflect globally enabled Rx and Tx offloads in queue conf. Also fix issue with lmt data prepare for multi seg. Fixes: a24af6361e37 ("net/cnxk: add Tx queue setup and release") Fixes: a86144cd9ded ("net/cnxk: add Rx queue setup and release") Fixes: 305ca2c4c382 ("net/cnxk: support multi-segment vector Tx") Cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_tx.h | 2 +- drivers/net/cnxk/cnxk_ethdev.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index ad84464..c6f349b 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -1280,7 +1280,7 @@ cn10k_nix_prep_lmt_mseg_vector(struct rte_mbuf **mbufs, uint64x2_t *cmd0, vst1q_u64(lmt_addr + 14, cmd1[3]); *data128 |= ((__uint128_t)7) << *shift; - shift += 3; + *shift += 3; return 1; } diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index fa9a26f..2683bc1 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -380,6 +380,8 @@ cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, txq_sp->dev = dev; txq_sp->qid = qid; txq_sp->qconf.conf.tx = *tx_conf; + /* Queue config should reflect global offloads */ + txq_sp->qconf.conf.tx.offloads = dev->tx_offloads; txq_sp->qconf.nb_desc = nb_desc; plt_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " lmt_addr=%p" @@ -527,6 +529,8 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, rxq_sp->dev = dev; rxq_sp->qid = qid; rxq_sp->qconf.conf.rx = *rx_conf; + /* Queue config should reflect global offloads */ + rxq_sp->qconf.conf.rx.offloads = dev->rx_offloads; rxq_sp->qconf.nb_desc = nb_desc; rxq_sp->qconf.mp = mp;