From patchwork Mon Oct 4 08:37:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 100417 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B45DBA0C4C; Mon, 4 Oct 2021 10:37:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2A7DA412ED; Mon, 4 Oct 2021 10:37:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A7A2E412E4 for ; Mon, 4 Oct 2021 10:37:48 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1948CIfA013065 for ; Mon, 4 Oct 2021 01:37:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=EuQMff9MKhEy5W/VHoX2CYURBTwryT0lj1ssUbvTVXY=; b=Dw6RIVaRgluD1SryKIYYqfs3sXzonBmNMCqM4Etw0U3+qnjYlhA19KVx//hfTkVSpqOk OkYohJePvuq8DQjj6LWY9A6H/UjETsvimXRdWWDrjHqX92lfenddcOAlac5wZM0z0E0q 2bo2NtPz5wJfKbKuHAulkuAXgKhQY3wk+XcxaHs+7mk1VjPRezZFhPVQzI1+xK1E3Fps G7mZ0mK5J/K+y0gJfi0hWJG2AbEolmj1igTS+p+f1LinO1gzICZ7VIE5SxGo6DJaAhEM yY9TffZ2J8hpWotM7lmfBxLFZpMxoG4fjEefgc0iObSEcQFrKZA5XCBAocq5rq/VHCkj kQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3bfc9ya35p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 04 Oct 2021 01:37:47 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 4 Oct 2021 01:37:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 4 Oct 2021 01:37:45 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 4E2AA3F7043; Mon, 4 Oct 2021 01:37:44 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Mon, 4 Oct 2021 14:07:37 +0530 Message-ID: <20211004083738.13386-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211004083738.13386-1-pbhagavatula@marvell.com> References: <20211004083738.13386-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: AQ0qgloIEbaGSwXJjbHEsReHxxDwIZQU X-Proofpoint-ORIG-GUID: AQ0qgloIEbaGSwXJjbHEsReHxxDwIZQU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-10-04_02,2021-10-01_02,2020-04-07_01 Subject: [dpdk-dev] [PATCH 2/3] event/cnxk: reduce workslot memory consumption X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh SSO group base addresses are always are always contiguous we need not store all the base addresses in workslot memory, instead just store the base address and compute the group address offset when required. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 5 ++--- drivers/event/cnxk/cn10k_worker.h | 3 ++- drivers/event/cnxk/cn9k_eventdev.c | 8 +++----- drivers/event/cnxk/cn9k_worker.h | 6 ++++-- drivers/event/cnxk/cnxk_eventdev.c | 15 ++++++--------- drivers/event/cnxk/cnxk_eventdev.h | 8 ++++---- 6 files changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index c2729a2c48..49bdd14208 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -91,14 +91,13 @@ cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link) } static void -cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) +cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base) { struct cnxk_sso_evdev *dev = arg; struct cn10k_sso_hws *ws = hws; uint64_t val; - rte_memcpy(ws->grps_base, grps_base, - sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); + ws->grp_base = grp_base; ws->fc_mem = (uint64_t *)dev->fc_iova; ws->xaq_lmt = dev->xaq_lmt; diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index 657ab91ac8..f8331e88d7 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -30,7 +30,8 @@ cn10k_sso_hws_new_event(struct cn10k_sso_hws *ws, const struct rte_event *ev) if (ws->xaq_lmt <= *ws->fc_mem) return 0; - cnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]); + cnxk_sso_hws_add_work(event_ptr, tag, new_tt, + ws->grp_base + (grp << 12)); return 1; } diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 3a20b099ae..9886720310 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -87,7 +87,7 @@ cn9k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link) } static void -cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) +cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base) { struct cnxk_sso_evdev *dev = arg; struct cn9k_sso_hws_dual *dws; @@ -98,8 +98,7 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) val = NSEC2USEC(dev->deq_tmo_ns) - 1; if (dev->dual_ws) { dws = hws; - rte_memcpy(dws->grps_base, grps_base, - sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); + dws->grp_base = grp_base; dws->fc_mem = (uint64_t *)dev->fc_iova; dws->xaq_lmt = dev->xaq_lmt; @@ -107,8 +106,7 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base) plt_write64(val, dws->base[1] + SSOW_LF_GWS_NW_TIM); } else { ws = hws; - rte_memcpy(ws->grps_base, grps_base, - sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP); + ws->grp_base = grp_base; ws->fc_mem = (uint64_t *)dev->fc_iova; ws->xaq_lmt = dev->xaq_lmt; diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 6be9be0b47..320e39da7b 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -31,7 +31,8 @@ cn9k_sso_hws_new_event(struct cn9k_sso_hws *ws, const struct rte_event *ev) if (ws->xaq_lmt <= *ws->fc_mem) return 0; - cnxk_sso_hws_add_work(event_ptr, tag, new_tt, ws->grps_base[grp]); + cnxk_sso_hws_add_work(event_ptr, tag, new_tt, + ws->grp_base + (grp << 12)); return 1; } @@ -108,7 +109,8 @@ cn9k_sso_hws_dual_new_event(struct cn9k_sso_hws_dual *dws, if (dws->xaq_lmt <= *dws->fc_mem) return 0; - cnxk_sso_hws_add_work(event_ptr, tag, new_tt, dws->grps_base[grp]); + cnxk_sso_hws_add_work(event_ptr, tag, new_tt, + dws->grp_base + (grp << 12)); return 1; } diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 84bf8cb6d1..c127034d37 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -332,8 +332,7 @@ cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, cnxk_sso_hws_setup_t hws_setup_fn) { struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); - uintptr_t grps_base[CNXK_SSO_MAX_HWGRP] = {0}; - uint16_t q; + uintptr_t grp_base = 0; plt_sso_dbg("Port=%d", port_id); if (event_dev->data->ports[port_id] == NULL) { @@ -341,15 +340,13 @@ cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id, return -EINVAL; } - for (q = 0; q < dev->nb_event_queues; q++) { - grps_base[q] = roc_sso_hwgrp_base_get(&dev->sso, q); - if (grps_base[q] == 0) { - plt_err("Failed to get grp[%d] base addr", q); - return -EINVAL; - } + grp_base = roc_sso_hwgrp_base_get(&dev->sso, 0); + if (grp_base == 0) { + plt_err("Failed to get grp base addr"); + return -EINVAL; } - hws_setup_fn(dev, event_dev->data->ports[port_id], grps_base); + hws_setup_fn(dev, event_dev->data->ports[port_id], grp_base); plt_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]); rte_mb(); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index ccd09b1d82..ce9f965691 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -61,7 +61,7 @@ } while (0) typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id); -typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base); +typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t grp_base); typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws); typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map, uint16_t nb_link); @@ -129,7 +129,7 @@ struct cn10k_sso_hws { /* Add Work Fastpath data */ uint64_t xaq_lmt __rte_cache_aligned; uint64_t *fc_mem; - uintptr_t grps_base[CNXK_SSO_MAX_HWGRP]; + uintptr_t grp_base; /* Tx Fastpath data */ uint64_t tx_base __rte_cache_aligned; uintptr_t lmt_base; @@ -157,7 +157,7 @@ struct cn9k_sso_hws { /* Add Work Fastpath data */ uint64_t xaq_lmt __rte_cache_aligned; uint64_t *fc_mem; - uintptr_t grps_base[CNXK_SSO_MAX_HWGRP]; + uintptr_t grp_base; /* Tx Fastpath data */ uint64_t base __rte_cache_aligned; uint8_t tx_adptr_data[]; @@ -179,7 +179,7 @@ struct cn9k_sso_hws_dual { /* Add Work Fastpath data */ uint64_t xaq_lmt __rte_cache_aligned; uint64_t *fc_mem; - uintptr_t grps_base[CNXK_SSO_MAX_HWGRP]; + uintptr_t grp_base; /* Tx Fastpath data */ uint64_t base[2] __rte_cache_aligned; uint8_t tx_adptr_data[];