From patchwork Tue Oct 26 15:39:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pradeep Nalla X-Patchwork-Id: 102941 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D9BD0A0547; Tue, 26 Oct 2021 17:40:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ED3B94113D; Tue, 26 Oct 2021 17:39:57 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4F4ED41135 for ; Tue, 26 Oct 2021 17:39:56 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 19QAMWP8014640 for ; Tue, 26 Oct 2021 08:39:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=MqwYrwvW4pyAlteDDZlZoa51/pSgXiHKWUGDzED8kRg=; b=PiZzfFVe7AU/ZXIdy2gkH5nGO4UgYWsR6AeoybbBTol6FDJUmb5o+ymXqoOpETgHu+j8 GLyT17iWAYkJr66ylmHyc3LUN60DEjslmzHvK6e1/zB2FsPwkYS3xPnXtFZyh5rIqVKy zWY+jyzl2480TOQJTT8ZEeV12W/s5OW0slnGPF/JA5zWG7gXbq4G/BnyNpu7JbcTtNUV xRjZyecyRabAXOrp01cR9C9yBwmF8s/33B6QwZF+0dEhO5JXXxjYzHx0SBWzr+8Hoe0M XjO1S9G0orCfydnqfJnc2TjLQCTVMZqsHSgvZ+YoiOaMMHy0NOIiYgKe9HPMVp5hig58 pQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3bxfv8hbj2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 26 Oct 2021 08:39:55 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 26 Oct 2021 08:39:53 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 26 Oct 2021 08:39:53 -0700 Received: from sophos1.caveonetworks.com (unknown [10.106.27.241]) by maili.marvell.com (Postfix) with ESMTP id 9C45F3F7072; Tue, 26 Oct 2021 08:39:53 -0700 (PDT) From: Pradeep Nalla To: Nalla Pradeep , Radha Mohan Chintakuntla , Veerasenareddy Burru CC: , , Date: Tue, 26 Oct 2021 08:39:33 -0700 Message-ID: <20211026153933.15467-1-pnalla@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-GUID: opPZ43LUQ9-kB86Y8pngmOCluXK-hG0v X-Proofpoint-ORIG-GUID: opPZ43LUQ9-kB86Y8pngmOCluXK-hG0v X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-10-26_04,2021-10-26_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH] net/octeontx_ep: Remove otx2 common dependency X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" octeontx_ep driver's dependency on octeontx2 common code is removed as going forward ep driver will include files from its own path. Signed-off-by: Pradeep Nalla --- drivers/net/octeontx_ep/meson.build | 2 - drivers/net/octeontx_ep/otx2_ep_vf.c | 13 +-- drivers/net/octeontx_ep/otx2_ep_vf.h | 112 ++++++++++++++++++++++++ drivers/net/octeontx_ep/otx_ep_common.h | 3 + drivers/net/octeontx_ep/otx_ep_ethdev.c | 1 - 5 files changed, 122 insertions(+), 9 deletions(-) diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build index 89f88caff0..b15646b82a 100644 --- a/drivers/net/octeontx_ep/meson.build +++ b/drivers/net/octeontx_ep/meson.build @@ -2,7 +2,6 @@ # Copyright(C) 2021 Marvell. # -deps += ['common_octeontx2'] sources = files( 'otx_ep_ethdev.c', 'otx_ep_rxtx.c', @@ -10,4 +9,3 @@ sources = files( 'otx2_ep_vf.c', ) -includes += include_directories('../../common/octeontx2') diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c index 64cd8731d3..0716beb9b1 100644 --- a/drivers/net/octeontx_ep/otx2_ep_vf.c +++ b/drivers/net/octeontx_ep/otx2_ep_vf.c @@ -2,7 +2,8 @@ * Copyright(C) 2021 Marvell. */ -#include "otx2_common.h" +#include +#include #include "otx_ep_common.h" #include "otx2_ep_vf.h" @@ -215,7 +216,7 @@ otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no) otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no)); - otx2_info("IQ[%d] enable done", q_no); + otx_ep_info("IQ[%d] enable done", q_no); return 0; } @@ -229,7 +230,7 @@ otx2_vf_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no) reg_val |= 0x1ull; otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no)); - otx2_info("OQ[%d] enable done", q_no); + otx_ep_info("OQ[%d] enable done", q_no); return 0; } @@ -326,10 +327,10 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep) if (otx_ep->conf == NULL) { otx_ep->conf = otx2_ep_get_defconf(otx_ep); if (otx_ep->conf == NULL) { - otx2_err("SDP VF default config not found"); + otx_ep_err("SDP VF default config not found"); return -ENOENT; } - otx2_info("Default config is used"); + otx_ep_info("Default config is used"); } /* Get IOQs (RPVF] count */ @@ -338,7 +339,7 @@ otx2_ep_vf_setup_device(struct otx_ep_device *otx_ep) otx_ep->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS) & SDP_VF_R_IN_CTL_RPVF_MASK); - otx2_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf); + otx_ep_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf); otx_ep->fn_list.setup_iq_regs = otx2_vf_setup_iq_regs; otx_ep->fn_list.setup_oq_regs = otx2_vf_setup_oq_regs; diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.h b/drivers/net/octeontx_ep/otx2_ep_vf.h index 5e5aefbc1c..9326925025 100644 --- a/drivers/net/octeontx_ep/otx2_ep_vf.h +++ b/drivers/net/octeontx_ep/otx2_ep_vf.h @@ -4,6 +4,118 @@ #ifndef _OTX2_EP_VF_H_ #define _OTX2_EP_VF_H_ +#include + +#define SDP_VF_R_IN_CTL_IDLE (0x1ull << 28) +#define SDP_VF_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */ +#define SDP_VF_R_IN_CTL_IS_64B (0x1ull << 24) +#define SDP_VF_R_IN_CTL_ESR (0x1ull << 1) + +#define SDP_VF_BUSY_LOOP_COUNT (10000) + +/* SDP VF OQ Masks */ +#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40) +#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34) +#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33) +#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32) +#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30) +#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29) +#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28) +#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26) +#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25) +#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24) +#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23) + +/* SDP VF Register definitions */ +#define SDP_VF_RING_OFFSET (0x1ull << 17) + +/* SDP VF IQ Registers */ +#define SDP_VF_R_IN_CONTROL_START (0x10000) +#define SDP_VF_R_IN_ENABLE_START (0x10010) +#define SDP_VF_R_IN_INSTR_BADDR_START (0x10020) +#define SDP_VF_R_IN_INSTR_RSIZE_START (0x10030) +#define SDP_VF_R_IN_INSTR_DBELL_START (0x10040) +#define SDP_VF_R_IN_CNTS_START (0x10050) +#define SDP_VF_R_IN_INT_LEVELS_START (0x10060) +#define SDP_VF_R_IN_PKT_CNT_START (0x10080) +#define SDP_VF_R_IN_BYTE_CNT_START (0x10090) + +#define SDP_VF_R_IN_CONTROL(ring) \ + (SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_IN_ENABLE(ring) \ + (SDP_VF_R_IN_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_IN_INSTR_BADDR(ring) \ + (SDP_VF_R_IN_INSTR_BADDR_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_IN_INSTR_RSIZE(ring) \ + (SDP_VF_R_IN_INSTR_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_IN_INSTR_DBELL(ring) \ + (SDP_VF_R_IN_INSTR_DBELL_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_IN_CNTS(ring) \ + (SDP_VF_R_IN_CNTS_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_IN_INT_LEVELS(ring) \ + (SDP_VF_R_IN_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_IN_PKT_CNT(ring) \ + (SDP_VF_R_IN_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_IN_BYTE_CNT(ring) \ + (SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET)) + +/* SDP VF OQ Registers */ +#define SDP_VF_R_OUT_CNTS_START (0x10100) +#define SDP_VF_R_OUT_INT_LEVELS_START (0x10110) +#define SDP_VF_R_OUT_SLIST_BADDR_START (0x10120) +#define SDP_VF_R_OUT_SLIST_RSIZE_START (0x10130) +#define SDP_VF_R_OUT_SLIST_DBELL_START (0x10140) +#define SDP_VF_R_OUT_CONTROL_START (0x10150) +#define SDP_VF_R_OUT_ENABLE_START (0x10160) +#define SDP_VF_R_OUT_PKT_CNT_START (0x10180) +#define SDP_VF_R_OUT_BYTE_CNT_START (0x10190) + +#define SDP_VF_R_OUT_CONTROL(ring) \ + (SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_OUT_ENABLE(ring) \ + (SDP_VF_R_OUT_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_OUT_SLIST_BADDR(ring) \ + (SDP_VF_R_OUT_SLIST_BADDR_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_OUT_SLIST_RSIZE(ring) \ + (SDP_VF_R_OUT_SLIST_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_OUT_SLIST_DBELL(ring) \ + (SDP_VF_R_OUT_SLIST_DBELL_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_OUT_CNTS(ring) \ + (SDP_VF_R_OUT_CNTS_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_OUT_INT_LEVELS(ring) \ + (SDP_VF_R_OUT_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_OUT_PKT_CNT(ring) \ + (SDP_VF_R_OUT_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET)) + +#define SDP_VF_R_OUT_BYTE_CNT(ring) \ + (SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET)) + +/* SDP VF IQ Masks */ +#define SDP_VF_R_IN_CTL_RPVF_MASK (0xF) +#define SDP_VF_R_IN_CTL_RPVF_POS (48) + +/* IO Access */ +#define otx2_read64(addr) rte_read64_relaxed((void *)(addr)) +#define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr)) + +#define PCI_DEVID_OCTEONTX2_EP_NET_VF 0xB203 /* OCTEON TX2 EP mode */ +#define PCI_DEVID_CN98XX_EP_NET_VF 0xB103 + int otx2_ep_vf_setup_device(struct otx_ep_device *sdpvf); diff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h index 5d0b30a1f0..fd5e8ed263 100644 --- a/drivers/net/octeontx_ep/otx_ep_common.h +++ b/drivers/net/octeontx_ep/otx_ep_common.h @@ -504,5 +504,8 @@ struct otx_ep_buf_free_info { #define OTX_EP_CLEAR_SLIST_DBELL 0xFFFFFFFF #define OTX_EP_CLEAR_SDP_OUT_PKT_CNT 0xFFFFFFFFF +/* PCI IDs */ +#define PCI_VENDOR_ID_CAVIUM 0x177D + extern int otx_net_ep_logtype; #endif /* _OTX_EP_COMMON_H_ */ diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c index 698d22e226..5e371595a5 100644 --- a/drivers/net/octeontx_ep/otx_ep_ethdev.c +++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c @@ -4,7 +4,6 @@ #include -#include "otx2_common.h" #include "otx_ep_common.h" #include "otx_ep_vf.h" #include "otx2_ep_vf.h"