From patchwork Tue Nov 2 15:54:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 103512 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 361D3A0C4E; Tue, 2 Nov 2021 16:54:38 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 697CE411B2; Tue, 2 Nov 2021 16:54:34 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 56FDA41158 for ; Tue, 2 Nov 2021 16:54:33 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1A2CjgHQ030466; Tue, 2 Nov 2021 08:54:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=bPJuyLjSV30IUtsX/myH8asNe016y0VDbiJiVt1gldU=; b=UAbESmmvKxJ3b6WN+GweLm+8+M0e1Xsg+HSvPIMvVdQdQTOhQGqm0bG6A0H+kEBWm0Rx NKe5ZMXkV/mXf2QymMref+CG1wBSKBdQqGITY2wBZlD6QFN8rBkJDa7t2TF9K/8uVNEB wZ+pkxvCHoW1fvkA0YMvlKHYhf/jyQRN4Yee0GgGcnLkTa1nB6ebxz1pn9SBbHcMp2jL 9ZC8X7xhGMDhP0nvBc4di7YXPPdjlUlb53H9mjBKaWn5ZQNbG2YxVaLcPHC1qszxLgms cZuWUVz7Tupm5p0PeWb3XQLJyK4fufQyE1Jv33cJsMGyaHzyHOZuxUiN3y2Zy6uRhxt+ ZA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3c35mbh5mq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 02 Nov 2021 08:54:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Tue, 2 Nov 2021 08:54:29 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id AEF195B6932; Tue, 2 Nov 2021 08:54:26 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Srujana Challa Date: Tue, 2 Nov 2021 21:24:13 +0530 Message-ID: <20211102155421.486-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211102155421.486-1-ndabilpuram@marvell.com> References: <20211102155421.486-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: MyWAY8Qb_-CvU-ieXCUWosEiWyi7KGra X-Proofpoint-ORIG-GUID: MyWAY8Qb_-CvU-ieXCUWosEiWyi7KGra X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-02_08,2021-11-02_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 2/9] common/cnxk: add CPT CTX sync mailbox API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Srujana Challa Add CPT CTX sync mailbox API and flush IPsec inbound entries at application exit. Signed-off-by: Srujana Challa --- drivers/common/cnxk/roc_mbox.h | 1 + drivers/common/cnxk/roc_nix.c | 14 ++++++++++++++ drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_inl.c | 3 +++ drivers/common/cnxk/roc_nix_inl_dev.c | 16 ++++++++++++++++ drivers/common/cnxk/version.map | 1 + 6 files changed, 36 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 22f6ebc..5dcb445 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -143,6 +143,7 @@ struct mbox_msghdr { M(CPT_STATS, 0xA05, cpt_sts_get, cpt_sts_req, cpt_sts_rsp) \ M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \ msg_rsp) \ + M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \ M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \ cpt_rx_inline_lf_cfg_msg, msg_rsp) \ M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \ diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 64156ce..949be80 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -109,6 +109,20 @@ roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct roc_nix_ipsec_cfg *cfg, } int +roc_nix_cpt_ctx_cache_sync(struct roc_nix *roc_nix) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct mbox *mbox = (&nix->dev)->mbox; + struct msg_req *req; + + req = mbox_alloc_msg_cpt_ctx_cache_sync(mbox); + if (req == NULL) + return -ENOSPC; + + return mbox_process(mbox); +} + +int roc_nix_max_pkt_len(struct roc_nix *roc_nix) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 343bb2f..d83a9b5 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -437,6 +437,7 @@ int __roc_api roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, int __roc_api roc_nix_lf_free(struct roc_nix *roc_nix); int __roc_api roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct roc_nix_ipsec_cfg *cfg, bool enb); +int __roc_api roc_nix_cpt_ctx_cache_sync(struct roc_nix *roc_nix); /* Debug */ int __roc_api roc_nix_lf_get_reg_count(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 3955d9b..f0fc690 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -258,6 +258,9 @@ roc_nix_inl_inb_fini(struct roc_nix *roc_nix) nix->inl_inb_ena = false; + /* Flush Inbound CTX cache entries */ + roc_nix_cpt_ctx_cache_sync(roc_nix); + /* Disable Inbound SA */ return nix_inl_sa_tbl_release(roc_nix); } diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 33a59f6..a0fe6ec 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -97,6 +97,19 @@ nix_inl_selftest(void) } static int +nix_inl_cpt_ctx_cache_sync(struct nix_inl_dev *inl_dev) +{ + struct mbox *mbox = (&inl_dev->dev)->mbox; + struct msg_req *req; + + req = mbox_alloc_msg_cpt_ctx_cache_sync(mbox); + if (req == NULL) + return -ENOSPC; + + return mbox_process(mbox); +} + +static int nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena) { struct nix_inline_ipsec_lf_cfg *lf_cfg; @@ -628,6 +641,9 @@ roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev) inl_dev = idev->nix_inl_dev; pci_dev = inl_dev->pci_dev; + /* Flush Inbound CTX cache entries */ + nix_inl_cpt_ctx_cache_sync(inl_dev); + /* Release SSO */ rc = nix_inl_sso_release(inl_dev); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index c2333a5..a90e5fc 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -149,6 +149,7 @@ INTERNAL { roc_nix_inl_ctx_write; roc_nix_inl_inb_sa_init; roc_nix_inl_outb_sa_init; + roc_nix_cpt_ctx_cache_sync; roc_nix_is_lbk; roc_nix_is_pf; roc_nix_is_sdp;