From patchwork Wed Nov 3 07:58:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xueming Li X-Patchwork-Id: 103618 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8B559A0C55; Wed, 3 Nov 2021 09:00:23 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 49931411B2; Wed, 3 Nov 2021 08:59:54 +0100 (CET) Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam08on2044.outbound.protection.outlook.com [40.107.101.44]) by mails.dpdk.org (Postfix) with ESMTP id B837E41183 for ; Wed, 3 Nov 2021 08:59:51 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=N3ZH0IjOpVvpP1P4/lOa6f0ZS7Weifs5vxRGaj0ERKejunALLXqg0QG32L+FxS29rlw6h4WR/6xa2Z0XcwUGx4Jo3i6xBkcyb/FdysEQLLXplyaD5yY/pCxitJpGdn+rAiw2xRaPvHUOfLqgkW+Lai2JpvjiUUkYNWu+D+7KN36pQAm9lM3Kz5yDLGG+qDZ5RVlbqNgA7t3esP+ThK8Qrs9IrXatZSRTGAkLYX9vMj+3uHRdoag9yCy7GV70KGjdb+ztMh1IBW+WUepQQgVhCuMeiDQyUzkAcsc11BsUdAjcWdSYzHijEUpdryqGGOXaPR32dvlgb2JS8xYjRdwaxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=uLQSQNFbKX2avp9PwWs+Fklik6xxGABufP/UofbdiKA=; b=Ln1YrCJ3kQdA6gLTnP7sVXbf6oFLKsz77DAXH8iuUDGOtcXPg8uQNn8KN62OU4OSnqqpLYd/q5jnb3UYfVIIuGQSo1YLKPcc0TygYlyzmO0+QBnIJq9yNCd5fV1ubsRc61BhP52VchLQh9gU/hawsAhzCx3D+cLCSeF/ksxc2JnrCHddPVObKVkhiAkQwAaFMtOGXUY/0UAjm6YHPSVseWbfo+EUMwGNx9gpVOs7y4kRHjWXzPGJkGgZT0pW3lYj/1mwzu5MeGQzeWEVzG92jQ8e2/1tHjJCjp0HCF99od4kJHcsPZw9o4TClktUMVKb3FkqaNYg0WdUmMDdCs4qfQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uLQSQNFbKX2avp9PwWs+Fklik6xxGABufP/UofbdiKA=; b=qzTDi2SaxGEW1jGQR6BKafQIFCOt60Oizk7vU7G3gGwNGtc8ccs+pyAR/z6pQMEMNYrCfMthYzgch4P3xeySQQuIfEOyairZ5vOmIl0GUtM/sZuAOn6sxl8yyqvGbdouBHd1sf7NxGgBQOGhA9Ny2lDE0qhxKDqNcidbBrwzVS1/hSmXci0JIAP9gjw4/mm89YAWzUxJpPoXCwLP7J0nOXLD73czUJgDIu0dpuOTGLicDMhTzRxvN+F8Im4/YtwFmYpc5AhP7sirydI9cEnt7jRuBFfA5/YgmCPXFM5EbBsgzKKIFlnBIUi6JGxjviXC71Nl7U4jXJep68ftt7QZfg== Received: from MWHPR12CA0043.namprd12.prod.outlook.com (2603:10b6:301:2::29) by DM5PR12MB4677.namprd12.prod.outlook.com (2603:10b6:4:a4::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.11; Wed, 3 Nov 2021 07:59:49 +0000 Received: from CO1NAM11FT054.eop-nam11.prod.protection.outlook.com (2603:10b6:301:2:cafe::5c) by MWHPR12CA0043.outlook.office365.com (2603:10b6:301:2::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4649.15 via Frontend Transport; Wed, 3 Nov 2021 07:59:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT054.mail.protection.outlook.com (10.13.174.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Wed, 3 Nov 2021 07:59:49 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 3 Nov 2021 07:59:47 +0000 From: Xueming Li To: CC: , Lior Margalit , Matan Azrad , Viacheslav Ovsiienko Date: Wed, 3 Nov 2021 15:58:33 +0800 Message-ID: <20211103075838.1486056-10-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211103075838.1486056-1-xuemingl@nvidia.com> References: <20210727034204.20649-1-xuemingl@nvidia.com> <20211103075838.1486056-1-xuemingl@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: eacedf78-c549-41fd-be92-08d99e9fe8f7 X-MS-TrafficTypeDiagnostic: DM5PR12MB4677: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:295; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4KAOizK66d9+y7zLsgc40caGp8RvA11gT/F9g6xoa51ZEX66tX51zuut13RIHH3r5yNP620JPu3QgBDysChjDubhyult3FXHvYVtMYQOYDtXI9JyO/h3IVsy7DjS2SyPmV5SInCyZigm8NIM84Z2DuIoZkAJhtcGmyCbyXH7CXELR6fh+lUDf4ZoFNP8PPPNoUyHtZviA8y4FYFKGgHHHeeh2M1FFd4FYP99eMfYW7H6AVVAw6OAY1vk5RH/T5R0wLyBk4r1lVrJmaBkqWm77mkUz43CweuG01iXncQdnrDkHHoACb0ibB+k3BSSh8ETt42kzSji3obzvTlNeGNOwmOeD1sjChBq/ZzRqmXj/yKIiZCHOHEOsZM2NC6i+JB3cQr89CYs21pYcVP/HXGcbKnHALh8jSI6Tckyc7FdDZNWbDlExu1JtzcUGpqhXHeuYT1cMqPefr1cCInbdRO7EvgLpdS0qegk9KQVTZZMWLtst8vUBqGsABj7riEEeLMHBDDIQ3pwzaVIgpV6Tlo0oPnPVFepCC87Mxmki97KQXZ8AJ7piGOjaQ0X0xnuKykPyx7AGk6ptQxHW2yDVZuku90dvFPeNf/G2FUFQhM5fuk4MsIFsnHioy07A8q4PzcOFn85QRsHXfraitWmU3QvIUqTq12KGXzDp3sRYCXGzuZo1lONaDA5N97uBFJU4md0vyQLJwKUeCiUBHebqa50Qg== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(6666004)(70586007)(1076003)(2906002)(2616005)(356005)(86362001)(7696005)(47076005)(107886003)(82310400003)(186003)(5660300002)(54906003)(8676002)(6286002)(16526019)(508600001)(316002)(7636003)(83380400001)(55016002)(26005)(6916009)(36860700001)(4326008)(426003)(70206006)(336012)(8936002)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2021 07:59:49.3525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eacedf78-c549-41fd-be92-08d99e9fe8f7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB4677 Subject: [dpdk-dev] [PATCH v3 09/14] net/mlx5: move Rx queue hairpin info to private data X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hairpin info of Rx queue can't be shared, moves to private queue data. Signed-off-by: Xueming Li --- drivers/net/mlx5/mlx5_rx.h | 4 ++-- drivers/net/mlx5/mlx5_rxq.c | 13 +++++-------- drivers/net/mlx5/mlx5_trigger.c | 24 ++++++++++++------------ 3 files changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index eccfbf1108d..b21918223b8 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -162,8 +162,6 @@ struct mlx5_rxq_ctrl { uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */ uint32_t wqn; /* WQ number. */ uint16_t dump_file_n; /* Number of dump files. */ - struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ - uint32_t hairpin_status; /* Hairpin binding status. */ }; /* RX queue private data. */ @@ -173,6 +171,8 @@ struct mlx5_rxq_priv { struct mlx5_rxq_ctrl *ctrl; /* Shared Rx Queue. */ LIST_ENTRY(mlx5_rxq_priv) owner_entry; /* Entry in shared rxq_ctrl. */ struct mlx5_priv *priv; /* Back pointer to private data. */ + struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ + uint32_t hairpin_status; /* Hairpin binding status. */ }; /* mlx5_rxq.c */ diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 8071ddbd61c..7b637fda643 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -1695,8 +1695,8 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, tmpl->rxq.elts_n = log2above(desc); tmpl->rxq.elts = NULL; tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 }; - tmpl->hairpin_conf = *hairpin_conf; tmpl->rxq.idx = idx; + rxq->hairpin_conf = *hairpin_conf; mlx5_rxq_ref(dev, idx); LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next); return tmpl; @@ -1913,14 +1913,11 @@ const struct rte_eth_hairpin_conf * mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx) { struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_rxq_ctrl *rxq_ctrl = NULL; + struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx); - if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) { - rxq_ctrl = container_of((*priv->rxqs)[idx], - struct mlx5_rxq_ctrl, - rxq); - if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) - return &rxq_ctrl->hairpin_conf; + if (idx < priv->rxqs_n && rxq != NULL) { + if (rxq->ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) + return &rxq->hairpin_conf; } return NULL; } diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index e5d74d275f8..a124f74fcda 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -324,7 +324,7 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev) } rxq_ctrl = rxq->ctrl; if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN || - rxq_ctrl->hairpin_conf.peers[0].queue != i) { + rxq->hairpin_conf.peers[0].queue != i) { rte_errno = ENOMEM; DRV_LOG(ERR, "port %u Tx queue %d can't be binded to " "Rx queue %d", dev->data->port_id, @@ -354,7 +354,7 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev) if (ret) goto error; /* Qs with auto-bind will be destroyed directly. */ - rxq_ctrl->hairpin_status = 1; + rxq->hairpin_status = 1; txq_ctrl->hairpin_status = 1; mlx5_txq_release(dev, i); } @@ -457,9 +457,9 @@ mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, } peer_info->qp_id = rxq_ctrl->obj->rq->id; peer_info->vhca_id = priv->config.hca_attr.vhca_id; - peer_info->peer_q = rxq_ctrl->hairpin_conf.peers[0].queue; - peer_info->tx_explicit = rxq_ctrl->hairpin_conf.tx_explicit; - peer_info->manual_bind = rxq_ctrl->hairpin_conf.manual_bind; + peer_info->peer_q = rxq->hairpin_conf.peers[0].queue; + peer_info->tx_explicit = rxq->hairpin_conf.tx_explicit; + peer_info->manual_bind = rxq->hairpin_conf.manual_bind; } return 0; } @@ -581,20 +581,20 @@ mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, dev->data->port_id, cur_queue); return -rte_errno; } - if (rxq_ctrl->hairpin_status != 0) { + if (rxq->hairpin_status != 0) { DRV_LOG(DEBUG, "port %u Rx queue %d is already bound", dev->data->port_id, cur_queue); return 0; } if (peer_info->tx_explicit != - rxq_ctrl->hairpin_conf.tx_explicit) { + rxq->hairpin_conf.tx_explicit) { rte_errno = EINVAL; DRV_LOG(ERR, "port %u Rx queue %d and peer Tx rule mode" " mismatch", dev->data->port_id, cur_queue); return -rte_errno; } if (peer_info->manual_bind != - rxq_ctrl->hairpin_conf.manual_bind) { + rxq->hairpin_conf.manual_bind) { rte_errno = EINVAL; DRV_LOG(ERR, "port %u Rx queue %d and peer binding mode" " mismatch", dev->data->port_id, cur_queue); @@ -606,7 +606,7 @@ mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, rq_attr.hairpin_peer_vhca = peer_info->vhca_id; ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr); if (ret == 0) - rxq_ctrl->hairpin_status = 1; + rxq->hairpin_status = 1; } return ret; } @@ -688,7 +688,7 @@ mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, dev->data->port_id, cur_queue); return -rte_errno; } - if (rxq_ctrl->hairpin_status == 0) { + if (rxq->hairpin_status == 0) { DRV_LOG(DEBUG, "port %u Rx queue %d is already unbound", dev->data->port_id, cur_queue); return 0; @@ -703,7 +703,7 @@ mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, rq_attr.rq_state = MLX5_SQC_STATE_RST; ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr); if (ret == 0) - rxq_ctrl->hairpin_status = 0; + rxq->hairpin_status = 0; } return ret; } @@ -1041,7 +1041,7 @@ mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, rxq_ctrl = rxq->ctrl; if (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN) continue; - pp = rxq_ctrl->hairpin_conf.peers[0].port; + pp = rxq->hairpin_conf.peers[0].port; if (pp >= RTE_MAX_ETHPORTS) { rte_errno = ERANGE; DRV_LOG(ERR, "port %hu queue %u peer port "