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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT016.mail.protection.outlook.com (10.13.176.97) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Mon, 8 Nov 2021 14:12:12 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 8 Nov 2021 14:11:47 +0000 From: Viacheslav Ovsiienko To: CC: , , Date: Mon, 8 Nov 2021 16:11:31 +0200 Message-ID: <20211108141131.16128-1-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 680dd6b3-d94b-4b0c-f3d2-08d9a2c1c2bf X-MS-TrafficTypeDiagnostic: DM6PR12MB3436: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(54906003)(36756003)(186003)(83380400001)(6916009)(8676002)(70206006)(6666004)(316002)(36906005)(36860700001)(8936002)(7636003)(16526019)(6286002)(2906002)(356005)(26005)(107886003)(336012)(508600001)(7696005)(70586007)(5660300002)(82310400003)(86362001)(47076005)(1076003)(55016002)(4326008)(2616005)(426003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Nov 2021 14:12:12.7614 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 680dd6b3-d94b-4b0c-f3d2-08d9a2c1c2bf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT016.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3436 Subject: [dpdk-dev] [PATCH 1/1] net/mlx5: fix modify field action conversion mask X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The routine converting RTE flow modify field action into field driver's presentation did not specify the field mask correctly and this resulted into wrong conversion for the actions with shifted fields. Fixes: 40c8fb1fd3b3 ("net/mlx5: update modify field action") Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 46 ++++++++++++++++----------------- 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 842ada2ea9..de7923e288 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1470,11 +1470,11 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){2, 4, MLX5_MODI_OUT_DMAC_15_0}; if (width < 16) { - mask[idx] = rte_cpu_to_be_16(0xffff >> + mask[1] = rte_cpu_to_be_16(0xffff >> (16 - width)); width = 0; } else { - mask[idx] = RTE_BE16(0xffff); + mask[1] = RTE_BE16(0xffff); width -= 16; } if (!width) @@ -1483,8 +1483,8 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_DMAC_47_16}; - mask[idx] = rte_cpu_to_be_32((0xffffffff >> - (32 - width)) << off); + mask[0] = rte_cpu_to_be_32((0xffffffff >> + (32 - width)) << off); } else { if (data->offset < 16) info[idx++] = (struct field_modify_info){2, 4, @@ -1500,11 +1500,11 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){2, 4, MLX5_MODI_OUT_SMAC_15_0}; if (width < 16) { - mask[idx] = rte_cpu_to_be_16(0xffff >> + mask[1] = rte_cpu_to_be_16(0xffff >> (16 - width)); width = 0; } else { - mask[idx] = RTE_BE16(0xffff); + mask[1] = RTE_BE16(0xffff); width -= 16; } if (!width) @@ -1513,8 +1513,8 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_SMAC_47_16}; - mask[idx] = rte_cpu_to_be_32((0xffffffff >> - (32 - width)) << off); + mask[0] = rte_cpu_to_be_32((0xffffffff >> + (32 - width)) << off); } else { if (data->offset < 16) info[idx++] = (struct field_modify_info){2, 4, @@ -1582,12 +1582,12 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 12, MLX5_MODI_OUT_SIPV6_31_0}; if (width < 32) { - mask[idx] = + mask[3] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); width = 0; } else { - mask[idx] = RTE_BE32(0xffffffff); + mask[3] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1598,12 +1598,12 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 8, MLX5_MODI_OUT_SIPV6_63_32}; if (width < 32) { - mask[idx] = + mask[2] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); width = 0; } else { - mask[idx] = RTE_BE32(0xffffffff); + mask[2] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1614,12 +1614,12 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 4, MLX5_MODI_OUT_SIPV6_95_64}; if (width < 32) { - mask[idx] = + mask[1] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); width = 0; } else { - mask[idx] = RTE_BE32(0xffffffff); + mask[1] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1628,8 +1628,7 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_SIPV6_127_96}; - mask[idx] = rte_cpu_to_be_32(0xffffffff >> - (32 - width)); + mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 12, @@ -1651,12 +1650,12 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 12, MLX5_MODI_OUT_DIPV6_31_0}; if (width < 32) { - mask[idx] = + mask[3] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); width = 0; } else { - mask[idx] = RTE_BE32(0xffffffff); + mask[3] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1667,12 +1666,12 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 8, MLX5_MODI_OUT_DIPV6_63_32}; if (width < 32) { - mask[idx] = + mask[2] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); width = 0; } else { - mask[idx] = RTE_BE32(0xffffffff); + mask[2] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1683,12 +1682,12 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){4, 4, MLX5_MODI_OUT_DIPV6_95_64}; if (width < 32) { - mask[idx] = + mask[1] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); width = 0; } else { - mask[idx] = RTE_BE32(0xffffffff); + mask[1] = RTE_BE32(0xffffffff); width -= 32; } if (!width) @@ -1697,8 +1696,7 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){4, 0, MLX5_MODI_OUT_DIPV6_127_96}; - mask[idx] = rte_cpu_to_be_32(0xffffffff >> - (32 - width)); + mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 12,