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Thu, 27 Jan 2022 07:40:19 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 13/20] net/mlx5: add E-switch mode flag Date: Thu, 27 Jan 2022 17:39:43 +0200 Message-ID: <20220127153950.812953-14-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127153950.812953-1-michaelba@nvidia.com> References: <20220127153950.812953-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d74374d7-d6ea-46c8-cc03-08d9e1ab540d X-MS-TrafficTypeDiagnostic: MWHPR12MB1279:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /wkLZVW8L1p6pVxEgFbQx+I5ykTBf7Ukkc9J2CZ3bi82qv0NjJM6HPh132FKjgv3w7HlSUCUKFFZBEzn3sY1drA98g9XnGJ0frCupboyZDoqqKRSvcPntP5xpRqhFnDl2UUDtYa2Y6SIDa7yhKgvHHMZSjDlc5ujOPahruBsgGMdAgJm1JxMnR8qGhATqiS0qhuefm5Mg7IEoU1mf27F3CtnUgmDxIzyo3m+hXd9DkiP3G6EYsQamrH+fJ/w01EWRs76AXdMvLjpinPGVr3EOEByTLxfxjBWJ0JUoOleGEVyti86bdnY+F8TaXwxBAoufOa4OjJb3SXceKM+ynaLFSW6XpHxIVu+48+DH/BOTdOsdAqJ1NTRYNR8XeVTsE7eM05UgSgTCGL5UQVqLlvIHJVVPIW1a4fw7gwz721KFbQJR7mvBUCpStmsb0p7Cep/h/G3oMj36elCTgSu99eFw41bGfMC0edIuOn5V+NsX2L2z7RMrItf2uzooLhpz/131q1RFiceUFWki6g2uAh3xk8ZfL8Inb8gaXTylLEkfZOz6gStHI97zX7dh1NPpaYl6UlNoy6sv/1ahWUcxzu72DTM2FnDNj/pg5XksSJklLvOvsRrhnsijS+RO8o7bwSCErWlU4ftVDXDje/FZB7BQTCNUppGdwsoUQqn2tmLqTdGvy7ivotu1eXR8mVjwEWdoKsbPjDQRR7bFCA8ELE66YWK12sM2cZuT2A8T5QxdwguIHc/J4KkLyHvZ43m0jgUc+sGFslOCleRqvPo9pUK2z1Om5JzO0IUwJUp6dgkbvQ= X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(4636009)(40470700004)(46966006)(36840700001)(47076005)(6666004)(86362001)(36860700001)(40460700003)(36756003)(81166007)(4326008)(26005)(6916009)(70206006)(55016003)(5660300002)(82310400004)(70586007)(83380400001)(426003)(508600001)(54906003)(316002)(2906002)(356005)(6286002)(1076003)(107886003)(8936002)(8676002)(336012)(186003)(7696005)(2616005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 15:40:21.3764 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d74374d7-d6ea-46c8-cc03-08d9e1ab540d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1279 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds in SH structure a flag which indicates whether is E-Switch mode. When configure "dv_esw_en" from devargs, it is enabled only when is E-switch mode. So, since dv_esw_en has been configure, it is enough to check if "dv_esw_en" is valid. This patch also removes E-Switch mode check when "dv_esw_en" is checked too. Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_os.c | 14 +++++--------- drivers/net/mlx5/mlx5.c | 1 + drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_ethdev.c | 4 ++-- drivers/net/mlx5/mlx5_flow_dv.c | 12 +++--------- drivers/net/mlx5/mlx5_trigger.c | 5 ++--- 6 files changed, 14 insertions(+), 23 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 9a05c1ba44..47b088db83 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -951,10 +951,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, if (!sh) return NULL; /* Update final values for devargs before check sibling config. */ - if (config->dv_miss_info) { - if (switch_info->master || switch_info->representor) - config->dv_xmeta_en = MLX5_XMETA_MODE_META16; - } #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) if (config->dv_flow_en) { DRV_LOG(WARNING, "DV flow is not supported."); @@ -962,12 +958,13 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } #endif #ifdef HAVE_MLX5DV_DR_ESWITCH - if (!(hca_attr->eswitch_manager && config->dv_flow_en && - (switch_info->representor || switch_info->master))) + if (!(hca_attr->eswitch_manager && config->dv_flow_en && sh->esw_mode)) config->dv_esw_en = 0; #else config->dv_esw_en = 0; #endif + if (config->dv_miss_info && config->dv_esw_en) + config->dv_xmeta_en = MLX5_XMETA_MODE_META16; if (!config->dv_esw_en && config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { DRV_LOG(WARNING, @@ -1133,7 +1130,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, * register to match on vport index. The engaged part of metadata * register is defined by mask. */ - if (switch_info->representor || switch_info->master) { + if (sh->esw_mode) { err = mlx5_glue->devx_port_query(sh->cdev->ctx, spawn->phys_port, &vport_info); @@ -1164,8 +1161,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, } if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) { priv->vport_id = vport_info.vport_id; - } else if (spawn->pf_bond >= 0 && - (switch_info->representor || switch_info->master)) { + } else if (spawn->pf_bond >= 0 && sh->esw_mode) { DRV_LOG(ERR, "Cannot deduce vport index for port %d on bonding device %s", spawn->phys_port, spawn->phys_dev_name); diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 27bcca9012..e1fe8f9375 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1259,6 +1259,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, pthread_mutex_init(&sh->txpp.mutex, NULL); sh->numa_node = spawn->cdev->dev->numa_node; sh->cdev = spawn->cdev; + sh->esw_mode = !!(spawn->info.master || spawn->info.representor); if (spawn->bond_info) sh->bond = *spawn->bond_info; err = mlx5_os_get_dev_attr(sh->cdev, &sh->device_attr); diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index d69b6a357b..a713e61572 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1146,6 +1146,7 @@ struct mlx5_flex_item { struct mlx5_dev_ctx_shared { LIST_ENTRY(mlx5_dev_ctx_shared) next; uint32_t refcnt; + uint32_t esw_mode:1; /* Whether is E-Switch mode. */ uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ uint32_t steering_format_version:4; /* Indicates the device steering logic format. */ diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 801c467bba..06d5acb75f 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -672,7 +672,7 @@ mlx5_port_to_eswitch_info(uint16_t port, bool valid) } dev = &rte_eth_devices[port]; priv = dev->data->dev_private; - if (!(priv->representor || priv->master)) { + if (!priv->sh->esw_mode) { rte_errno = EINVAL; return NULL; } @@ -699,7 +699,7 @@ mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev) struct mlx5_priv *priv; priv = dev->data->dev_private; - if (!(priv->representor || priv->master)) { + if (!priv->sh->esw_mode) { rte_errno = EINVAL; return NULL; } diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 4e60a54df3..6a5ac01c2a 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -6600,11 +6600,6 @@ flow_dv_validate_attributes(struct rte_eth_dev *dev, (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, "E-Switch dr is not supported"); - if (!(priv->representor || priv->master)) - return rte_flow_error_set - (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, - NULL, "E-Switch configuration can only be" - " done by a master or a representor device"); if (attributes->egress) return rte_flow_error_set (error, ENOTSUP, @@ -13612,8 +13607,7 @@ flow_dv_translate(struct rte_eth_dev *dev, * E-Switch rule where no port_id item was found. In both cases * the source port is set according the current port in use. */ - if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && - (priv->representor || priv->master)) { + if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && priv->sh->esw_mode) { if (flow_dv_translate_item_port_id(dev, match_mask, match_value, NULL, attr)) return -rte_errno; @@ -16173,7 +16167,7 @@ __flow_dv_create_policy_flow(struct rte_eth_dev *dev, struct mlx5_priv *priv = dev->data->dev_private; uint8_t misc_mask; - if (match_src_port && (priv->representor || priv->master)) { + if (match_src_port && priv->sh->esw_mode) { if (flow_dv_translate_item_port_id(dev, matcher.buf, value.buf, item, attr)) { DRV_LOG(ERR, "Failed to create meter policy%d flow's" @@ -16225,7 +16219,7 @@ __flow_dv_create_policy_matcher(struct rte_eth_dev *dev, struct mlx5_priv *priv = dev->data->dev_private; const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1; - if (match_src_port && (priv->representor || priv->master)) { + if (match_src_port && priv->sh->esw_mode) { if (flow_dv_translate_item_port_id(dev, matcher.mask.buf, value.buf, item, attr)) { DRV_LOG(ERR, "Failed to register meter policy%d matcher" diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 1dfe7da435..d128b3e978 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1330,8 +1330,7 @@ mlx5_traffic_enable(struct rte_eth_dev *dev) goto error; } } - if ((priv->representor || priv->master) && - priv->config.dv_esw_en) { + if (priv->config.dv_esw_en) { if (mlx5_flow_create_devx_sq_miss_flow(dev, i) == 0) { DRV_LOG(ERR, "Port %u Tx queue %u SQ create representor devx default miss rule failed.", @@ -1341,7 +1340,7 @@ mlx5_traffic_enable(struct rte_eth_dev *dev) } mlx5_txq_release(dev, i); } - if ((priv->master || priv->representor) && priv->config.dv_esw_en) { + if (priv->config.dv_esw_en) { if (mlx5_flow_create_esw_table_zero_flow(dev)) priv->fdb_def_rule = 1; else