From patchwork Mon Jan 31 12:30:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 106737 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B3D2FA04A2; Mon, 31 Jan 2022 12:39:37 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 97E31411B2; Mon, 31 Jan 2022 12:39:37 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B4F584069D for ; Mon, 31 Jan 2022 12:39:35 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20VBHNkf003800 for ; Mon, 31 Jan 2022 03:39:35 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=j+StJBuY0l2fRKrGXYNsXk+qzKQkRmm04ickhxiGlaE=; b=hl/qan+jYr1uT82wiejrjo88dB6GrTcSxwN7/kcrIaDurxIF/rcF0gVEQaCPBVNq+dCF +/aevoCJRvdaLqxXA0dH6a2+D3kPeF592zXwhyrqvlRWJkKuw6K4p9Yg27o8KadwkU0W 38bzkz4ssPAQkA+V52oNHaY7/Ii7EdVGeO56fIJVovQG71CuokZkvx9kzwOO/PgfjXyg Xx1P3xbo99LZ8WL68ui4XSStQPuSTh5nK2MGHG/XDWHTNZXzXPIVrfq0gTx/zgUCM6J0 DpY1Tw9lytddbl1S+6PG2MeydYFFiWy3yzN7GqFt7f9QuVjjXtliLsqm4wwIbK3vlrp5 bA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3dw5yqm8nh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 31 Jan 2022 03:39:34 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 31 Jan 2022 03:39:33 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 31 Jan 2022 03:39:33 -0800 Received: from hyd1554T5810.caveonetworks.com.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id CE7D73F703F; Mon, 31 Jan 2022 03:39:30 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Ankur Dwivedi , Archana Muniganti , Tejasree Kondoj , Subject: [PATCH 5/5] crypto/cnxk: fix updation of number of descriptors Date: Mon, 31 Jan 2022 18:00:29 +0530 Message-ID: <20220131123029.4024-6-ktejasree@marvell.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220131123029.4024-1-ktejasree@marvell.com> References: <20220131123029.4024-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: IHK4BYsBnQa0IljirV262Fl8OVrbo6WR X-Proofpoint-GUID: IHK4BYsBnQa0IljirV262Fl8OVrbo6WR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Anoob Joseph Pending queue also need to be adjusted while updating the number of descriptors. Fixes: a455fd869cd7 ("common/cnxk: align CPT queue depth to power of 2") Cc: anoobj@marvell.com Signed-off-by: Anoob Joseph --- drivers/common/cnxk/roc_cpt.c | 3 --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 8 ++++++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c index 1bc7a29ef9..4e24850366 100644 --- a/drivers/common/cnxk/roc_cpt.c +++ b/drivers/common/cnxk/roc_cpt.c @@ -568,9 +568,6 @@ cpt_lf_init(struct roc_cpt_lf *lf) if (lf->nb_desc == 0 || lf->nb_desc > CPT_LF_MAX_NB_DESC) lf->nb_desc = CPT_LF_DEFAULT_NB_DESC; - /* Update nb_desc to next power of 2 to aid in pending queue checks */ - lf->nb_desc = plt_align32pow2(lf->nb_desc); - /* Allocate memory for instruction queue for CPT LF. */ iq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN); if (iq_mem == NULL) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 67a2d9b08e..a5fb68da02 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -361,6 +361,7 @@ cnxk_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, struct roc_cpt *roc_cpt = &vf->cpt; struct rte_pci_device *pci_dev; struct cnxk_cpt_qp *qp; + uint32_t nb_desc; int ret; if (dev->data->queue_pairs[qp_id] != NULL) @@ -373,14 +374,17 @@ cnxk_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, return -EIO; } - qp = cnxk_cpt_qp_create(dev, qp_id, conf->nb_descriptors); + /* Update nb_desc to next power of 2 to aid in pending queue checks */ + nb_desc = plt_align32pow2(conf->nb_descriptors); + + qp = cnxk_cpt_qp_create(dev, qp_id, nb_desc); if (qp == NULL) { plt_err("Could not create queue pair %d", qp_id); return -ENOMEM; } qp->lf.lf_id = qp_id; - qp->lf.nb_desc = conf->nb_descriptors; + qp->lf.nb_desc = nb_desc; ret = roc_cpt_lf_init(roc_cpt, &qp->lf); if (ret < 0) {