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Mon, 14 Feb 2022 01:00:21 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko Subject: [PATCH 2/2] net/mlx5: optimize RxQ creation Date: Mon, 14 Feb 2022 11:00:10 +0200 Message-ID: <20220214090010.1541746-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220214090010.1541746-1-michaelba@nvidia.com> References: <20220214090010.1541746-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6a862e39-faf9-41aa-6fc8-08d9ef986fef X-MS-TrafficTypeDiagnostic: BN9PR12MB5353:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: N9i0QtQSjFXgL5suzqu+TaQVxOQhLXlO0Gjg/SaDlwqRk2IscejmP8TCNao8fLKejcLdZVg1xtZd7rHHs+vnDUlkNFODxsTJWkI6FQU9dhilC4B+pjBoaKz5oa46P+9kWRUrj+j9K89qfkFKeVk3IAOmuC6biTvVwZpGgG7LFMVOF3HwsBfL/b1pX4VFwoC9T5e0vy3FzBZg6YLfrQAlvFOmQfxjDz2Lgesd6MZw0W7o7HoeMXk+Xn8TJPGTzf2WMsMOyMWJSkxnS7CiuPGA83Ou/ICaqS//rzPhNL1Z3TrQ4rfkkzIhznZtX8I5EWbHF7NXDALy3Uhqh++PZC5XpM4ozOpU0xvRMlHG6hGnQXVSIvasLVbnY5oBi6dqHdSMdgP07+pUsuAmAtef7L8640mifrMtl3Up9xXBIyy6s9tM2u8N18tRl9Z7kEBdAbBMZrZurhF34/Es9SkW2+4XO0YkAFs52BdUrhVBJiw8VLnZ80+waPVl1jQv/1yk/ZJ1d/EyoqgVJPU+5OSF3eZvNqMvb9ku9VUuJkbVDpvEUSFak+o1ddJjl05gad8ctOK5JtuVo3Jhrrg5LPb1vF4BnradPk4TGsR73rWwCNbUJ7AZskkAR5KobC4xG/AWmP7ddI/h47fIuKt3NZjqPlZwLdh7Y2528WsZ51t5uk3BX40TUQqILmrOqxIy1ET6t2Hazs087saJWEvdM8Q6VNHd+w== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(336012)(6916009)(54906003)(426003)(316002)(82310400004)(8936002)(70586007)(86362001)(70206006)(8676002)(4326008)(356005)(26005)(6286002)(7696005)(107886003)(2616005)(81166007)(186003)(2906002)(47076005)(1076003)(508600001)(83380400001)(36860700001)(55016003)(36756003)(40460700003)(5660300002)(6666004)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 09:00:24.0416 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6a862e39-faf9-41aa-6fc8-08d9ef986fef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5353 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Recently shared RxQ has been introduced. All shared Rx queues with same group and queue ID share the same rxq_ctrl, but each one has mlx5_rxq_priv structure. The mlx5_rx_queue_setup generates a new rxq_priv structure, and looks for a rxq_ctrl structure to refer to. If there is already a compatible rxq_ctrl structure it refers it, otherwise it calls the mlx5_rxq_new function that generates a new one. This patch makes mlx5_rxq_new function "standalone", it generates a rxq_ctrl structure regardless to specific rxq_priv structure. All operations on the rxq_ctrl structure that depend on the new rxq_priv structure are performed in the mlx5_rx_queue_setup function, at the same place for either a new rxq_ctrl structure or an existing rxq_ctrl structure. Signed-off-by: Michael Baum Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_rx.h | 3 +-- drivers/net/mlx5/mlx5_rxq.c | 28 +++++++++++----------------- 2 files changed, 12 insertions(+), 19 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 7e417819f7..38335fd744 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -204,8 +204,7 @@ void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev); int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id); int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id); int mlx5_rxq_obj_verify(struct rte_eth_dev *dev); -struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, - struct mlx5_rxq_priv *rxq, +struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_rxconf *conf, const struct rte_eth_rxseg_split *rx_seg, diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index fe72cf49d3..eaa48487cc 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -910,25 +910,23 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, rte_errno = ENOMEM; return -rte_errno; } - rxq->priv = priv; - rxq->idx = idx; - (*priv->rxq_privs)[idx] = rxq; - if (rxq_ctrl != NULL) { - /* Join owner list. */ - LIST_INSERT_HEAD(&rxq_ctrl->owners, rxq, owner_entry); - rxq->ctrl = rxq_ctrl; - } else { - rxq_ctrl = mlx5_rxq_new(dev, rxq, desc, socket, conf, rx_seg, + if (rxq_ctrl == NULL) { + rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, rx_seg, n_seg); if (rxq_ctrl == NULL) { DRV_LOG(ERR, "port %u unable to allocate rx queue index %u", dev->data->port_id, idx); mlx5_free(rxq); - (*priv->rxq_privs)[idx] = NULL; rte_errno = ENOMEM; return -rte_errno; } } + rxq->priv = priv; + rxq->idx = idx; + (*priv->rxq_privs)[idx] = rxq; + /* Join owner list. */ + LIST_INSERT_HEAD(&rxq_ctrl->owners, rxq, owner_entry); + rxq->ctrl = rxq_ctrl; mlx5_rxq_ref(dev, idx); DRV_LOG(DEBUG, "port %u adding Rx queue %u to list", dev->data->port_id, idx); @@ -1660,8 +1658,8 @@ mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, * * @param dev * Pointer to Ethernet device. - * @param rxq - * RX queue private data. + * @param idx + * RX queue index. * @param desc * Number of descriptors to configure in queue. * @param socket @@ -1671,12 +1669,10 @@ mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, * A DPDK queue object on success, NULL otherwise and rte_errno is set. */ struct mlx5_rxq_ctrl * -mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, - uint16_t desc, +mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, const struct rte_eth_rxconf *conf, const struct rte_eth_rxseg_split *rx_seg, uint16_t n_seg) { - uint16_t idx = rxq->idx; struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_rxq_ctrl *tmpl; unsigned int mb_len = rte_pktmbuf_data_room_size(rx_seg[0].mp); @@ -1719,8 +1715,6 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, return NULL; } LIST_INIT(&tmpl->owners); - rxq->ctrl = tmpl; - LIST_INSERT_HEAD(&tmpl->owners, rxq, owner_entry); MLX5_ASSERT(n_seg && n_seg <= MLX5_MAX_RXQ_NSEG); /* * Save the original segment configuration in the shared queue