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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by DM6NAM11FT020.mail.protection.outlook.com (10.13.172.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5164.19 via Frontend Transport; Mon, 18 Apr 2022 11:10:22 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Mon, 18 Apr 2022 11:10:21 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 18 Apr 2022 04:10:20 -0700 From: Raja Zidane To: CC: Subject: [PATCH 1/2] common/mlx5: extend crypto capabilities Date: Mon, 18 Apr 2022 14:10:04 +0300 Message-ID: <20220418111005.2291-2-rzidane@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20220418111005.2291-1-rzidane@nvidia.com> References: <20220418111005.2291-1-rzidane@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dd8f7423-90eb-4c91-2e44-08da212c080f X-MS-TrafficTypeDiagnostic: MN2PR12MB3023:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Apr 2022 11:10:22.2586 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd8f7423-90eb-4c91-2e44-08da212c080f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3023 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Crypto capabilities struct contains info about crypto import method (wrapped/plaintext DEK) for each of the supported algorithms. Query crypto capabilities struct and save import methods. Signed-off-by: Raja Zidane --- drivers/common/mlx5/mlx5_devx_cmds.c | 13 +++++++++++-- drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 29 ++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index d02ac2a678..c6bdbc12bb 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -964,12 +964,21 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time); attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); - if (attr->crypto) - attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, general_obj_types) & MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); + if (attr->crypto) { + attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_CRYPTO | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) + return -1; + attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, + hcattr, wrapped_import_method) + & 1 << 2); + } if (hca_cap_2_sup) { hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 1bac18c59d..3747ef9e33 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -254,6 +254,7 @@ struct mlx5_hca_attr { uint32_t umr_indirect_mkey_disabled:1; uint32_t log_min_stride_wqe_sz:5; uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */ + uint32_t crypto_wrapped_import_method:1; uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ uint16_t max_wqe_sz_sq; }; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 44b18225f6..d04c9e32c9 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1293,6 +1293,7 @@ enum { MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1, MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, + MLX5_GET_HCA_CAP_OP_MOD_CRYPTO = 0x1A << 1, MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, }; @@ -3794,6 +3795,34 @@ struct mlx5_ifc_crypto_operational_register_bits { u8 reserved_at_280[0x180]; }; +struct mlx5_ifc_crypto_caps_bits { + u8 wrapped_crypto_operational[0x1]; + u8 wrapped_crypto_going_to_commissioning[0x1]; + u8 sw_wrapped_dek[0x1]; + u8 synchronize_dek[0x1]; + u8 int_kek_manual[0x1]; + u8 int_kek_auto[0x1]; + u8 reserved_at_6[0x12]; + u8 wrapped_import_method[0x8]; + u8 reserved_at_20[0x3]; + u8 log_dek_max_alloc[0x5]; + u8 reserved_at_28[0x3]; + u8 log_max_num_deks[0x5]; + u8 reserved_at_30[0x3]; + u8 log_max_num_import_keks[0x5]; + u8 reserved_at_38[0x3]; + u8 log_max_num_creds[0x5]; + u8 failed_selftests[0x10]; + u8 num_nv_import_keks[0x8]; + u8 num_nv_credentials[0x8]; + u8 reserved_at_60[0x3]; + u8 log_dek_granularity[0x5]; + u8 reserved_at_68[0x3]; + u8 log_max_num_int_kek[0x5]; + u8 reserved_at_70[0x10]; + u8 reserved_at_80[0x780]; +}; + struct mlx5_ifc_crypto_commissioning_register_bits { u8 token[0x1]; /* TODO: add size after PRM update */ };