From patchwork Fri Apr 29 09:19:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 110461 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 97B81A0093; Fri, 29 Apr 2022 03:22:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 228CC4282B; Fri, 29 Apr 2022 03:22:30 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 04AE64281C for ; Fri, 29 Apr 2022 03:22:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651195344; x=1682731344; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0p6zks75Mo867icsNU85Q8yLBOYrAwdOlwpopWmZEg0=; b=XgqLa8Xq+yJyuYBSL0nxn5r8TDaoME8l86F9ks9qSAVp6UPxAinZkBhE HuOehTzQCG9OQfwUiA6BDyyqFkuu906pyZEyFUtA6Ss+i4hJhjkXS9DdW LQnUKa+YxfWEkWAoCasuJ3NDkDHNoHATnYdOfJHw5dk4gm1fjYgYz6Ysn leFviWmQvF2pWjZqay8d+Aqb5ooJasm10aOKIwRS8kW0+BM6N5ZrMFTfQ yUPqrxyGSHScUJRdH30s4U3y8TSuyJ3vqg0KVG5i8dRjSHZ8LiJV4Fuet mtnfLRaOyC63C47q4xy7OR3KOSDRjo8tk4rxrstkcoR1pnJUki/acNGMW A==; X-IronPort-AV: E=McAfee;i="6400,9594,10331"; a="266013650" X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="266013650" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 18:22:23 -0700 X-IronPort-AV: E=Sophos;i="5.91,296,1647327600"; d="scan'208";a="581767776" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2022 18:22:21 -0700 From: Kevin Liu To: dev@dpdk.org Cc: qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH v7 02/12] net/ice: support for RSS HASH configure in DCF mode Date: Fri, 29 Apr 2022 09:19:48 +0000 Message-Id: <20220429091958.3103384-3-kevinx.liu@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220429091958.3103384-1-kevinx.liu@intel.com> References: <20220427181301.1414196-1-kevinx.liu@intel.com> <20220429091958.3103384-1-kevinx.liu@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Steve Yang RSS HASH should be updated and queried by application, Add related ops ('.rss_hash_update', '.rss_hash_conf_get') for DCF. Because DCF doesn't support configure RSS HASH, only HASH key can be updated within ops '.rss_hash_update'. Signed-off-by: Steve Yang Signed-off-by: Kevin Liu --- doc/guides/nics/features/ice_dcf.ini | 1 + doc/guides/rel_notes/release_22_07.rst | 1 + drivers/net/ice/ice_dcf.c | 2 +- drivers/net/ice/ice_dcf.h | 1 + drivers/net/ice/ice_dcf_ethdev.c | 51 ++++++++++++++++++++++++++ 5 files changed, 55 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/ice_dcf.ini b/doc/guides/nics/features/ice_dcf.ini index 5221c99a9c..d9c1b25407 100644 --- a/doc/guides/nics/features/ice_dcf.ini +++ b/doc/guides/nics/features/ice_dcf.ini @@ -16,6 +16,7 @@ L4 checksum offload = P Inner L3 checksum = P Inner L4 checksum = P RSS reta update = Y +RSS key update = Y Basic stats = Y Linux = Y x86-32 = Y diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index 1f07d3e1b3..866af8c0b3 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -63,6 +63,7 @@ New Features * **Updated Intel ice driver.** * Added support for RSS RETA configure in DCF mode. + * Added support for RSS HASH configure in DCF mode. Removed Items ------------- diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c index 070d1b71ac..89c0203ba3 100644 --- a/drivers/net/ice/ice_dcf.c +++ b/drivers/net/ice/ice_dcf.c @@ -758,7 +758,7 @@ ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw) hw->ets_config = NULL; } -static int +int ice_dcf_configure_rss_key(struct ice_dcf_hw *hw) { struct virtchnl_rss_key *rss_key; diff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h index b2c6aa2684..f0b45af5ae 100644 --- a/drivers/net/ice/ice_dcf.h +++ b/drivers/net/ice/ice_dcf.h @@ -122,6 +122,7 @@ int ice_dcf_send_aq_cmd(void *dcf_hw, struct ice_aq_desc *desc, int ice_dcf_handle_vsi_update_event(struct ice_dcf_hw *hw); int ice_dcf_init_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); void ice_dcf_uninit_hw(struct rte_eth_dev *eth_dev, struct ice_dcf_hw *hw); +int ice_dcf_configure_rss_key(struct ice_dcf_hw *hw); int ice_dcf_configure_rss_lut(struct ice_dcf_hw *hw); int ice_dcf_init_rss(struct ice_dcf_hw *hw); int ice_dcf_configure_queues(struct ice_dcf_hw *hw); diff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c index 1ac66ed990..ccad7fc304 100644 --- a/drivers/net/ice/ice_dcf_ethdev.c +++ b/drivers/net/ice/ice_dcf_ethdev.c @@ -836,6 +836,55 @@ ice_dcf_dev_rss_reta_query(struct rte_eth_dev *dev, return 0; } +static int +ice_dcf_dev_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) + return -ENOTSUP; + + /* HENA setting, it is enabled by default, no change */ + if (!rss_conf->rss_key || rss_conf->rss_key_len == 0) { + PMD_DRV_LOG(DEBUG, "No key to be configured"); + return 0; + } else if (rss_conf->rss_key_len != hw->vf_res->rss_key_size) { + PMD_DRV_LOG(ERR, "The size of hash key configured " + "(%d) doesn't match the size of hardware can " + "support (%d)", rss_conf->rss_key_len, + hw->vf_res->rss_key_size); + return -EINVAL; + } + + rte_memcpy(hw->rss_key, rss_conf->rss_key, rss_conf->rss_key_len); + + return ice_dcf_configure_rss_key(hw); +} + +static int +ice_dcf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct ice_dcf_adapter *adapter = dev->data->dev_private; + struct ice_dcf_hw *hw = &adapter->real_hw; + + if (!(hw->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RSS_PF)) + return -ENOTSUP; + + /* Just set it to default value now. */ + rss_conf->rss_hf = ICE_RSS_OFFLOAD_ALL; + + if (!rss_conf->rss_key) + return 0; + + rss_conf->rss_key_len = hw->vf_res->rss_key_size; + rte_memcpy(rss_conf->rss_key, hw->rss_key, rss_conf->rss_key_len); + + return 0; +} + #define ICE_DCF_32_BIT_WIDTH (CHAR_BIT * 4) #define ICE_DCF_48_BIT_WIDTH (CHAR_BIT * 6) #define ICE_DCF_48_BIT_MASK RTE_LEN2MASK(ICE_DCF_48_BIT_WIDTH, uint64_t) @@ -1184,6 +1233,8 @@ static const struct eth_dev_ops ice_dcf_eth_dev_ops = { .tm_ops_get = ice_dcf_tm_ops_get, .reta_update = ice_dcf_dev_rss_reta_update, .reta_query = ice_dcf_dev_rss_reta_query, + .rss_hash_update = ice_dcf_dev_rss_hash_update, + .rss_hash_conf_get = ice_dcf_dev_rss_hash_conf_get, }; static int