From patchwork Wed Jun 22 06:56:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 113223 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6B283A04FD; Wed, 22 Jun 2022 08:48:45 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 53CE242B6E; Wed, 22 Jun 2022 08:48:26 +0200 (CEST) Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by mails.dpdk.org (Postfix) with ESMTP id EC66842823 for ; Wed, 22 Jun 2022 08:48:22 +0200 (CEST) X-QQ-mid: bizesmtp66t1655880494t3rj2844 Received: from wxdbg.localdomain.com ( [183.129.236.74]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 22 Jun 2022 14:48:13 +0800 (CST) X-QQ-SSF: 01400000002000F0Q000B00A0000000 X-QQ-FEAT: 3u0oYPVhaeMZSqMS51syWg1ajYydTN6C1BlT5RdoQDPws35N5o9tiS+Nn4+3t iiWHH/uU2XVpKgZo2u1QZBdhSMdsyrT/MpKxhD2nPetXWIeD3XKw/iRvLtXIa3Du8Vh8eYu 0MDql9tSXTRJArtnGd56mbNVJznVsuKPx7s8NeTwupKfRjm1vgR/5qqoszX8NS1FWwShO74 sdCGiw0mvVMzyEGp0WNQf3RRq7dghBb64vVz/rp0uR9yJ1/9QPw8jevVOXiXFGV7QVjqyq1 cYdUZ6xylaTMRazcg/XBphxx+tAWWeW++J0VqytK0BdPtHz8pQEacQ5wWZJKXqw51zXAYFB L/Xok7c5WQ4AqwUTrvnkONBz9opcia1QI0SNYFJjkzEEe0eWko= X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: Jiawen Wu , stable@dpdk.org Subject: [PATCH v2 5/7] net/ngbe: fix YT PHY UTP mode to link up Date: Wed, 22 Jun 2022 14:56:11 +0800 Message-Id: <20220622065613.661679-6-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220622065613.661679-1-jiawenwu@trustnetic.com> References: <20220622065613.661679-1-jiawenwu@trustnetic.com> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign3 X-QQ-Bgrelay: 1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix to read and write the correct register fields for yt8521s and yt8531s PHY, since mode check was added. Fixes: 1c44384fce76 ("net/ngbe: support custom PHY interfaces") Cc: stable@dpdk.org Signed-off-by: Jiawen Wu --- drivers/net/ngbe/base/ngbe_phy_yt.c | 42 ++++++++++++++--------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c index f46121b8d1..9dd2b2264f 100644 --- a/drivers/net/ngbe/base/ngbe_phy_yt.c +++ b/drivers/net/ngbe/base/ngbe_phy_yt.c @@ -146,21 +146,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* duplex full */ value |= YT_BCR_DUPLEX | YT_BCR_RESET; - hw->phy.write_reg(hw, YT_BCR, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); goto skip_an; } /*disable 100/10base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF); - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /*disable 1000base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF); - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); if (speed & NGBE_LINK_SPEED_1GB_FULL) { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL; @@ -176,19 +176,19 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* enable 1000base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value |= value_r9; - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); /* enable 100/10base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value |= value_r4; - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /* software reset to make the above configuration take effect*/ - hw->phy.read_reg(hw, YT_BCR, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN; - hw->phy.write_reg(hw, YT_BCR, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); skip_an: hw->phy.set_phy_power(hw, true); } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) { @@ -219,15 +219,15 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } else { /* utp up */ /*disable 100/10base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value &= ~(YT_ANA_100BASET_FULL | YT_ANA_100BASET_HALF | YT_ANA_10BASET_FULL | YT_ANA_10BASET_HALF); - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /*disable 1000base-T Self-negotiation ability*/ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value &= ~(YT_MS_1000BASET_FULL | YT_MS_1000BASET_HALF); - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); if (speed & NGBE_LINK_SPEED_1GB_FULL) { hw->phy.autoneg_advertised |= @@ -246,21 +246,21 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed, } /* enable 1000base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_MS_CTRL, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_MS_CTRL, 0, &value); value |= value_r9; - hw->phy.write_reg(hw, YT_MS_CTRL, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_MS_CTRL, 0, value); /* enable 100/10base-T Self-negotiation ability */ - hw->phy.read_reg(hw, YT_ANA, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_ANA, 0, &value); value |= value_r4; - hw->phy.write_reg(hw, YT_ANA, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_ANA, 0, value); /* software reset to make the above configuration * take effect */ - hw->phy.read_reg(hw, YT_BCR, 0, &value); + ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value); value |= YT_BCR_RESET; - hw->phy.write_reg(hw, YT_BCR, 0, value); + ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value); } } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(4)) { hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;