From patchwork Wed Jun 29 16:46:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Radu Nicolau X-Patchwork-Id: 113563 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 57D5DA034C; Wed, 29 Jun 2022 18:46:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3A0F540146; Wed, 29 Jun 2022 18:46:14 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id C84E840143 for ; Wed, 29 Jun 2022 18:46:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1656521173; x=1688057173; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=M7MUyribdGIlj5aKth6gMcEc6WsxR+sEVH8mtAVHDQI=; b=Zwmkh0JJ9CeBxM57NOwZ7n6FsJLa40iOWWCfofiN8vxuJyeWUgCnvkdr gV1hDnF/4qfA+xv1jpIBI8gGJfo/jh5gj2x+CwMW4NuU1M+LkJPyyoAJ9 GB+Fet1HIHmXyr+tlBRgkYwkcS9lmItjkG3bxKk5fjlvGBUVwmCtK8E+N NPKeMMy4E+tCZedzU6THd+zxJXajHY7ZAZYYRPmxxAXGZfbtP+qG+J1Uw qW7tFTtvNeihE31AGkzxuP3woYORJR7VUHxZYt9/JbsFPSk70dMqL1vfS s1AyEf1C8TtsZYnipuEfwLee4vyNJ/jbIGKyayziBMXA1foQThN11BDyr w==; X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="279624534" X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="279624534" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 09:46:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,231,1650956400"; d="scan'208";a="693653637" Received: from silpixa00400884.ir.intel.com ([10.243.22.82]) by fmsmga002.fm.intel.com with ESMTP; 29 Jun 2022 09:46:09 -0700 From: Radu Nicolau To: Radu Nicolau , Akhil Goyal Cc: dev@dpdk.org, roy.fan.zhang@intel.com, vladimir.medvedkin@intel.com, ndabilpuram@marvell.com Subject: [PATCH v2] examples/ipsec-secgw: fix Tx checksum offload flag Date: Wed, 29 Jun 2022 17:46:07 +0100 Message-Id: <20220629164607.2317125-1-radu.nicolau@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220622092808.1952992-1-radu.nicolau@intel.com> References: <20220622092808.1952992-1-radu.nicolau@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For the inline crypto path set the Tx checksum offload flag only if the device supports it. Fixes: d24471e5786b ("examples/ipsec-secgw: disable Tx checksum for inline") Cc: ndabilpuram@marvell.com Signed-off-by: Radu Nicolau Acked-by: Fan Zhang Acked-by: Akhil Goyal --- v2: when supported the checksum offload flag needs to also be set for ports that don't have SAs programmed examples/ipsec-secgw/sa.c | 44 ++++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/examples/ipsec-secgw/sa.c b/examples/ipsec-secgw/sa.c index 5d9cec97db..b364ac5881 100644 --- a/examples/ipsec-secgw/sa.c +++ b/examples/ipsec-secgw/sa.c @@ -1828,37 +1828,43 @@ sa_check_offloads(uint16_t port_id, uint64_t *rx_offloads, for (idx_sa = 0; idx_sa < nb_sa_out; idx_sa++) { rule = &sa_out[idx_sa]; rule_type = ipsec_get_action_type(rule); - switch (rule_type) { - case RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL: - /* Checksum offload is not needed for inline protocol as - * all processing for Outbound IPSec packets will be - * implicitly taken care and for non-IPSec packets, - * there is no need of IPv4 Checksum offload. - */ - if (rule->portid == port_id) { + if (rule->portid == port_id) { + switch (rule_type) { + case RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL: + /* Checksum offload is not needed for inline + * protocol as all processing for Outbound IPSec + * packets will be implicitly taken care and for + * non-IPSec packets, there is no need of + * IPv4 Checksum offload. + */ *tx_offloads |= RTE_ETH_TX_OFFLOAD_SECURITY; if (rule->mss) *tx_offloads |= (RTE_ETH_TX_OFFLOAD_TCP_TSO | RTE_ETH_TX_OFFLOAD_IPV4_CKSUM); - } - break; - case RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO: - if (rule->portid == port_id) { + break; + case RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO: *tx_offloads |= RTE_ETH_TX_OFFLOAD_SECURITY; if (rule->mss) *tx_offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO; - *tx_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; + if (dev_info.tx_offload_capa & + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) + *tx_offloads |= + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; + break; + default: + /* Enable IPv4 checksum offload even if + * one of lookaside SA's are present. + */ + if (dev_info.tx_offload_capa & + RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) + *tx_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; + break; } - break; - default: - /* Enable IPv4 checksum offload even if one of lookaside - * SA's are present. - */ + } else { if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) *tx_offloads |= RTE_ETH_TX_OFFLOAD_IPV4_CKSUM; - break; } } return 0;