From patchwork Thu Jul 7 10:47:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Liu X-Patchwork-Id: 113771 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5E0E2A0540; Thu, 7 Jul 2022 04:49:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DF96540A7B; Thu, 7 Jul 2022 04:49:38 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 101F9406B4 for ; Thu, 7 Jul 2022 04:49:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657162177; x=1688698177; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=RRXF/Tp2g/FmEkf2JrOqBr8CDOA8SKArlJpWQFSo8Oc=; b=hRMMIPjxXn6CSrj7L8RmUza7Ec4fLsx0fThmUifw1A2TaPsWOC/iu9Zr EztVjVJQtrcTvg/j6rxG/+zw2zi98FPgS/fIQBZuCAilNr5VvgxpKWFrB DWF/kWdUIP/U9yUVJ16MJZkGykszsk2qHakwQtxNUjeRYzVU+ueijnDBH Hkz75Upbq8+0RCq0tmEgJyoLfSFtaszKBCHLKCjOjjmtOUDrIbCjsnGAx ryJbaTdo/fPxmy8xH9AI973yLUz5oYKmY7nhV20Z+moMEO95OgJszawEN auOzDBkqPWmyrAA9NetphgKHtnuq5QjLQzLc0OKSDNbWklt5V/A9oi5lR Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10400"; a="370233295" X-IronPort-AV: E=Sophos;i="5.92,251,1650956400"; d="scan'208";a="370233295" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2022 19:49:35 -0700 X-IronPort-AV: E=Sophos;i="5.92,251,1650956400"; d="scan'208";a="650932205" Received: from intel-cd-odc-kevin.cd.intel.com ([10.240.178.191]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jul 2022 19:49:34 -0700 From: Kevin Liu To: dev@dpdk.org Cc: beilei.xing@intel.com, Yuying.Zhang@intel.com, stevex.yang@intel.com, Kevin Liu Subject: [PATCH] net/i40e: restore disable double VLAN by default Date: Thu, 7 Jul 2022 10:47:32 +0000 Message-Id: <20220707104732.1816933-1-kevinx.liu@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Restore disable double VLAN by default. Fixes: ae97b8b89826 ("net/i40e: fix error disable double VLAN") Signed-off-by: Kevin Liu Tested-by: Yu Jiang Tested-by: Yingya Han --- doc/guides/nics/i40e.rst | 6 +++--- drivers/net/i40e/i40e_ethdev.c | 12 ------------ 2 files changed, 3 insertions(+), 15 deletions(-) diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst index 85fdc4944d..f61c327726 100644 --- a/doc/guides/nics/i40e.rst +++ b/doc/guides/nics/i40e.rst @@ -969,10 +969,10 @@ it will fail and return the info "Conflict with the first rule's input set", which means the current rule's input set conflicts with the first rule's. Remove the first rule if want to change the input set of the PCTYPE. -Disable QinQ is not supported when FW >= 8.4 -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +To use VLAN functions, need to enable QinQ when FW >= 8.4 +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -If upgrade FW to version 8.4 and higher, enable QinQ by default and disable QinQ is not supported. +If upgrade FW to version 8.4 and higher, when using VLAN functions, need to enable QinQ. Example of getting best performance with l3fwd example diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 684e095026..117dd85c11 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -4027,12 +4027,6 @@ i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask) } if (mask & RTE_ETH_VLAN_EXTEND_MASK) { - /* Double VLAN not allowed to be disabled.*/ - if (pf->fw8_3gt && !(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)) { - PMD_DRV_LOG(WARNING, - "Disable double VLAN is not allowed after firmwarev8.3!"); - return 0; - } i = 0; num = vsi->mac_num; mac_filter = rte_zmalloc("mac_filter_info_data", @@ -6296,7 +6290,6 @@ int i40e_vsi_cfg_inner_vlan_stripping(struct i40e_vsi *vsi, bool on) static int i40e_dev_init_vlan(struct rte_eth_dev *dev) { - struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private); struct rte_eth_dev_data *data = dev->data; int ret; int mask = 0; @@ -6307,11 +6300,6 @@ i40e_dev_init_vlan(struct rte_eth_dev *dev) RTE_ETH_VLAN_FILTER_MASK | RTE_ETH_VLAN_EXTEND_MASK; - /* Double VLAN be enabled by default.*/ - if (pf->fw8_3gt) { - struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; - rxmode->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; - } ret = i40e_vlan_offload_set(dev, mask); if (ret) { PMD_DRV_LOG(INFO, "Failed to update vlan offload");