From patchwork Fri Aug 12 12:24:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Malov X-Patchwork-Id: 114918 X-Patchwork-Delegate: andrew.rybchenko@oktetlabs.ru Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0AD7CA0543; Fri, 12 Aug 2022 14:25:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BB3C42C00; Fri, 12 Aug 2022 14:25:00 +0200 (CEST) Received: from shelob.oktetlabs.ru (shelob.oktetlabs.ru [91.220.146.113]) by mails.dpdk.org (Postfix) with ESMTP id 561CC406A2 for ; Fri, 12 Aug 2022 14:24:57 +0200 (CEST) Received: from bree.oktetlabs.ru (bree.oktetlabs.ru [192.168.34.5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by shelob.oktetlabs.ru (Postfix) with ESMTPS id DE7A3B3; Fri, 12 Aug 2022 15:24:56 +0300 (MSK) DKIM-Filter: OpenDKIM Filter v2.11.0 shelob.oktetlabs.ru DE7A3B3 Authentication-Results: shelob.oktetlabs.ru/DE7A3B3; dkim=none; dkim-atps=neutral From: Ivan Malov To: dev@dpdk.org Cc: Andy Moreton , Andrew Rybchenko Subject: [PATCH 2/3] common/sfc_efx/base: report maximum Rx descriptor data count Date: Fri, 12 Aug 2022 15:24:53 +0300 Message-Id: <20220812122454.1947322-2-ivan.malov@oktetlabs.ru> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220812122454.1947322-1-ivan.malov@oktetlabs.ru> References: <20220812122454.1947322-1-ivan.malov@oktetlabs.ru> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Such information is useful to client drivers which deal with large Rx pool buffers (16-bit wide data count) and thus need to avoid overflow when setting EF10's 14-bit wide data count. Signed-off-by: Ivan Malov Reviewed-by: Andrew Rybchenko --- drivers/common/sfc_efx/base/ef10_nic.c | 1 + drivers/common/sfc_efx/base/efx.h | 1 + drivers/common/sfc_efx/base/efx_rx.c | 12 ++++++++++++ drivers/common/sfc_efx/base/rhead_nic.c | 4 ++++ drivers/common/sfc_efx/base/siena_nic.c | 1 + 5 files changed, 19 insertions(+) diff --git a/drivers/common/sfc_efx/base/ef10_nic.c b/drivers/common/sfc_efx/base/ef10_nic.c index 7bda778f8b..e1709d1200 100644 --- a/drivers/common/sfc_efx/base/ef10_nic.c +++ b/drivers/common/sfc_efx/base/ef10_nic.c @@ -2233,6 +2233,7 @@ ef10_nic_board_cfg( /* Alignment for WPTR updates */ encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; + encp->enc_rx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_TX_KER_BYTE_CNT); /* No boundary crossing limits */ encp->enc_tx_dma_desc_boundary = 0; diff --git a/drivers/common/sfc_efx/base/efx.h b/drivers/common/sfc_efx/base/efx.h index 95f5fb6bc0..ac26db3e57 100644 --- a/drivers/common/sfc_efx/base/efx.h +++ b/drivers/common/sfc_efx/base/efx.h @@ -1587,6 +1587,7 @@ typedef struct efx_nic_cfg_s { /* Number of rx descriptors the hardware requires for a push. */ uint32_t enc_rx_push_align; /* Maximum amount of data in DMA descriptor */ + uint32_t enc_rx_dma_desc_size_max; uint32_t enc_tx_dma_desc_size_max; /* * Boundary which DMA descriptor data must not cross or 0 if no diff --git a/drivers/common/sfc_efx/base/efx_rx.c b/drivers/common/sfc_efx/base/efx_rx.c index 45dc5d6c6d..68f42f5cac 100644 --- a/drivers/common/sfc_efx/base/efx_rx.c +++ b/drivers/common/sfc_efx/base/efx_rx.c @@ -978,7 +978,14 @@ efx_rx_qcreate( __in efx_evq_t *eep, __deref_out efx_rxq_t **erpp) { + const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp); efx_rxq_type_data_t type_data; + efx_rc_t rc; + + if (buf_size > encp->enc_rx_dma_desc_size_max) { + rc = EINVAL; + goto fail1; + } memset(&type_data, 0, sizeof (type_data)); @@ -986,6 +993,11 @@ efx_rx_qcreate( return efx_rx_qcreate_internal(enp, index, label, type, &type_data, esmp, ndescs, id, flags, eep, erpp); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); } #if EFSYS_OPT_RX_PACKED_STREAM diff --git a/drivers/common/sfc_efx/base/rhead_nic.c b/drivers/common/sfc_efx/base/rhead_nic.c index f2c18c1dcc..eda6c1c4f9 100644 --- a/drivers/common/sfc_efx/base/rhead_nic.c +++ b/drivers/common/sfc_efx/base/rhead_nic.c @@ -40,6 +40,10 @@ rhead_board_cfg( encp->enc_clk_mult = 1; /* not used for Riverhead */ + EFX_STATIC_ASSERT(MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN == 4); + /* Agrees with MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN */ + encp->enc_rx_dma_desc_size_max = UINT32_MAX; + /* * FIXME There are TxSend and TxSeg descriptors on Riverhead. * TxSeg is bigger than TxSend. diff --git a/drivers/common/sfc_efx/base/siena_nic.c b/drivers/common/sfc_efx/base/siena_nic.c index 939551dbf5..9f14faf271 100644 --- a/drivers/common/sfc_efx/base/siena_nic.c +++ b/drivers/common/sfc_efx/base/siena_nic.c @@ -146,6 +146,7 @@ siena_board_cfg( */ encp->enc_evq_init_done_ev_supported = B_TRUE; + encp->enc_rx_dma_desc_size_max = EFX_MASK32(FSF_AZ_RX_KER_BYTE_COUNT); encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT); /* Fragments must not span 4k boundaries. */ encp->enc_tx_dma_desc_boundary = 4096;