From patchwork Mon Aug 15 07:12:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 114986 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BAA77A00C3; Mon, 15 Aug 2022 01:06:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D525242C26; Mon, 15 Aug 2022 01:03:59 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 26B1C42BBD; Mon, 15 Aug 2022 01:03:58 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660518238; x=1692054238; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=J43I6398FsLaf+0CgJG9oYHwdzs/Fe3qvqKhitBSb1Q=; b=MJPLcH6t8HVhJkZQR3WiiLGdKchkaEaDGVM25atItXet3x3LEvHwKunR Hu815GBSo7a1XCRmAAUdS+unuJvQQmswVtSASoAzWJQEtQt6HkL7VbZMd twSYu96q6bFvyqroKZIb417JDDEU1E1UWk4nJeRBjUOLFsh40tAi4g2on Dv/yj9MOfpv+piInr89PDFtAcUnOb9mhakeyBhEWqBHgy7XhLPEfXgrrw t6b3ikexQ4azAGgwP130C+q3n+JNEtB1HhG7YrsP04qHEA4NmIF0r/LJg wJFT6AEXIIoKvuSdfzkP63x0a4r9Kcs94jNx66xsXfGzbDGezQBaD+PCK g==; X-IronPort-AV: E=McAfee;i="6400,9594,10439"; a="289427601" X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="289427601" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2022 16:03:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,237,1654585200"; d="scan'208";a="934296700" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4]) by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:03:56 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, Qi Zhang , stable@dpdk.org, Jesse Brandeburg Subject: [PATCH 29/70] net/ice/base: fix array overflow in add switch recipe code Date: Mon, 15 Aug 2022 03:12:25 -0400 Message-Id: <20220815071306.2910599-30-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220815071306.2910599-1-qi.z.zhang@intel.com> References: <20220815071306.2910599-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The array indexes in this function are used with a zero index in the fv_idx table, and with a +1 index in the lkup_idx arrays. The code was using the lookup index for the field vector in only one place in this function, but the code was never used after this point so just remove the bad line. This was caught by the undefined behavior sanitizer. Fixes: fed0c5ca5f19 ("net/ice/base: support programming a new switch recipe") Cc: stable@dpdk.org Signed-off-by: Jesse Brandeburg Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_switch.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index e59d191c46..b8e733f539 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -7315,7 +7315,6 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm, last_chain_entry->chain_idx = ICE_INVAL_CHAIN_IND; LIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry, l_entry) { - last_chain_entry->fv_idx[i] = entry->chain_idx; buf[recps].content.lkup_indx[i] = entry->chain_idx; buf[recps].content.mask[i++] = CPU_TO_LE16(0xFFFF); ice_set_bit(entry->rid, rm->r_bitmap);