From patchwork Wed Aug 17 06:08:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 115193 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B2C4BA0032; Wed, 17 Aug 2022 09:18:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6B85D427F7; Wed, 17 Aug 2022 09:17:55 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id C0FB1427E9 for ; Wed, 17 Aug 2022 09:17:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660720673; x=1692256673; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=IrbFjpr4puvaW38f2i6PI5bAsiNXJOkd/Yfn8m47P2M=; b=TGS8CMc9WX/5gQGm2pZegiq5hh2u+/n3MKtdP4hF/IAUdn77g5vkAEOo izKXUhd1OtBiRTXAR1Hv20vTLkVSSZLRhVsb1WR9+MZIbB8/X6PiJIcQd tnjkAsK39+LvsYhM0+3gon94T0qnyMsH2jCRXbA2Omn5yUhf5FGSJuA4T qfqvrAsiYi8np3WKhxhWP73bu3UGv+TES6TVQLtRPgO3kDT26D3pgYc+o oKMOHkqJ1Sns7foQlijRS89Yomk/Tb+YNKhOZTvqSNKINZhcDyaK1N1Jn 9nAVMqS41zHrPSJH/eASCf7IiwA7cmA7zMtPb1YD6SxDrBjoFVCS9qv6E g==; X-IronPort-AV: E=McAfee;i="6400,9594,10441"; a="356421133" X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="356421133" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2022 00:17:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="667485815" Received: from silpixa00399302.ir.intel.com ([10.237.214.136]) by fmsmga008.fm.intel.com with ESMTP; 17 Aug 2022 00:17:52 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, kai.ji@intel.com, Arek Kusztal Subject: [PATCH 4/4] crypto/qat : add SM3 hash algorithm Date: Wed, 17 Aug 2022 07:08:56 +0100 Message-Id: <20220817060856.78582-5-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20220817060856.78582-1-arkadiuszx.kusztal@intel.com> References: <20220817060856.78582-1-arkadiuszx.kusztal@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Added SM3 hash algorithm. Signed-off-by: Arek Kusztal --- doc/guides/cryptodevs/features/qat.ini | 1 + doc/guides/rel_notes/release_22_11.rst | 3 +++ drivers/common/qat/qat_adf/icp_qat_hw.h | 2 +- drivers/crypto/qat/qat_sym_session.c | 20 +++++++++++++++++++- 4 files changed, 24 insertions(+), 2 deletions(-) diff --git a/doc/guides/cryptodevs/features/qat.ini b/doc/guides/cryptodevs/features/qat.ini index edabc030d7..4508becc56 100644 --- a/doc/guides/cryptodevs/features/qat.ini +++ b/doc/guides/cryptodevs/features/qat.ini @@ -65,6 +65,7 @@ KASUMI F9 = Y AES XCBC MAC = Y ZUC EIA3 = Y AES CMAC (128) = Y +SM3 = Y ; ; Supported AEAD algorithms of the 'qat' crypto driver. diff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst index c6638ded82..5fb79f741c 100644 --- a/doc/guides/rel_notes/release_22_11.rst +++ b/doc/guides/rel_notes/release_22_11.rst @@ -69,6 +69,9 @@ New Features Added SM4 encryption algorithm to the QAT PMD. Supported modes are ECB, CBC and CTR. + Added SM3 hash algorithm to the QAT PMD. + + Removed Items ------------- diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h index b1e6a1fa15..f6875b5242 100644 --- a/drivers/common/qat/qat_adf/icp_qat_hw.h +++ b/drivers/common/qat/qat_adf/icp_qat_hw.h @@ -46,7 +46,7 @@ enum icp_qat_hw_auth_algo { ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12, ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13, ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14, - ICP_QAT_HW_AUTH_RESERVED_1 = 15, + ICP_QAT_HW_AUTH_ALGO_SM3 = 15, ICP_QAT_HW_AUTH_RESERVED_2 = 16, ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17, ICP_QAT_HW_AUTH_RESERVED_3 = 18, diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index f4e0faa8e1..6996c3499b 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -687,6 +687,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, session->digest_length = auth_xform->digest_length; switch (auth_xform->algo) { + case RTE_CRYPTO_AUTH_SM3: + session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SM3; + session->auth_mode = ICP_QAT_HW_AUTH_MODE2; + break; case RTE_CRYPTO_AUTH_SHA1: session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1; session->auth_mode = ICP_QAT_HW_AUTH_MODE0; @@ -1092,6 +1096,8 @@ static int qat_hash_get_block_size(enum icp_qat_hw_auth_algo qat_hash_alg) return ICP_QAT_HW_AES_BLK_SZ; case ICP_QAT_HW_AUTH_ALGO_MD5: return MD5_CBLOCK; + case ICP_QAT_HW_AUTH_ALGO_SM3: + return 64; case ICP_QAT_HW_AUTH_ALGO_DELIMITER: /* return maximum block size in this case */ return SHA512_CBLOCK; @@ -2035,7 +2041,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc, || cdesc->is_cnt_zero ) hash->auth_counter.counter = 0; - else { + else if (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE1) { int block_size = qat_hash_get_block_size(cdesc->qat_hash_alg); if (block_size < 0) @@ -2048,7 +2054,19 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc, /* * cd_cur_ptr now points at the state1 information. */ + uint8_t state1[] = { + 0x73, 0x80, 0x16, 0x6f, 0x49, 0x14, 0xb2, 0xb9, + 0x17, 0x24, 0x42, 0xd7, 0xda, 0x8a, 0x06, 0x00, + 0xa9, 0x6f, 0x30, 0xbc, 0x16, 0x31, 0x38, 0xaa, + 0xe3, 0x8d, 0xee, 0x4d, 0xb0, 0xfb, 0x0e, 0x4e + }; switch (cdesc->qat_hash_alg) { + case ICP_QAT_HW_AUTH_ALGO_SM3: + rte_memcpy(cdesc->cd_cur_ptr, state1, + sizeof(state1)); + state1_size = 32; + state2_size = 32; + break; case ICP_QAT_HW_AUTH_ALGO_SHA1: if (cdesc->auth_mode == ICP_QAT_HW_AUTH_MODE0) { /* Plain SHA-1 */