From patchwork Thu Oct 13 11:41:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118141 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1ABC5A00C2; Thu, 13 Oct 2022 13:42:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6EAD642EF7; Thu, 13 Oct 2022 13:42:13 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 6C28542EF7; Thu, 13 Oct 2022 13:42:12 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29D9IY4v010992; Thu, 13 Oct 2022 04:42:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=12CBqud154xdjddHvMclxiZ2HYHNCR5NR6QgPu1jU2I=; b=KPtWFvwMuNMtWAX52VhMWwvOj00x5dZMW94xhGDPZlMU062aaN0ZKzwsOHAQDg7QRmka ODQUrovIgj8UpPuDw2x3TLcqJlv8rauftmEQmHQuO4QxtwI1vJ60bmwLKQZzCX/UT655 P3XJgWav3u6QLpU/SMxF392SpSxgU1mYDUFWa/p0DxMAP0euNpTKIjzbK9P5EAlPO0yM hX2XQZve68HWyXg8krXR2xrZb4uVQ+xpyLSfLgk+uhmOp+PSUdcFHwldDuEvx5oq3/wx fl/ymoxMiZVWMFXRXcqiJFkKOBnA/KYqXNX94CYK/WdZC+6pNBT8LXf4HD0n0sPMUPtZ uA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k6fwv8edw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 13 Oct 2022 04:42:11 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 13 Oct 2022 04:42:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 04:42:09 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 713093F703F; Thu, 13 Oct 2022 04:42:07 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Subject: [PATCH v2 03/13] net/cnxk: fix later skip to include mbuf priv Date: Thu, 13 Oct 2022 17:11:46 +0530 Message-ID: <20221013114156.996517-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013114156.996517-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221013114156.996517-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Q3h5ISvw3KPnTqY3tRQIo5tiB_Xlj3GN X-Proofpoint-ORIG-GUID: Q3h5ISvw3KPnTqY3tRQIo5tiB_Xlj3GN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-13_08,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix later skip to include mbuf priv data as mbuf->buf_addr is populated based on calculation including per-mbuf priv area. Fixes: 706eeae60757 ("net/cnxk: add multi-segment Rx for CN10K") cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_rx.h | 4 +++- drivers/net/cnxk/cnxk_ethdev.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 46488d442e..cf390a0361 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -682,6 +682,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint64_t rearm, const uint16_t flags) { const rte_iova_t *iova_list; + uint16_t later_skip = 0; struct rte_mbuf *head; const rte_iova_t *eol; uint8_t nb_segs; @@ -720,10 +721,11 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, nb_segs--; rearm = rearm & ~0xFFFF; + later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf; head = mbuf; while (nb_segs) { - mbuf->next = ((struct rte_mbuf *)*iova_list) - 1; + mbuf->next = (struct rte_mbuf *)(*iova_list - later_skip); mbuf = mbuf->next; RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1); diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 71c3f1666b..bf1585fe67 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -680,7 +680,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, first_skip += RTE_PKTMBUF_HEADROOM; first_skip += rte_pktmbuf_priv_size(lpb_pool); rq->first_skip = first_skip; - rq->later_skip = sizeof(struct rte_mbuf); + rq->later_skip = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mp); rq->lpb_size = lpb_pool->elt_size; if (roc_errata_nix_no_meta_aura()) rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);