From patchwork Thu Oct 20 11:14:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 118781 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 79F4EA0552; Thu, 20 Oct 2022 13:15:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0ACF442D52; Thu, 20 Oct 2022 13:15:04 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E8D1642D4F for ; Thu, 20 Oct 2022 13:15:02 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29K6Qiaw010176 for ; Thu, 20 Oct 2022 04:15:02 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=rM/k8TjWNl6+Vzq5ch8nh23/Q/oKk84kCAnyLbjW0C4=; b=ZggHuFAn6GQQMW7fhtcwa5FNaBmrZ2c25SdlPaCpKAsl8ZqJ0VcpdFKE6r/tZocBk+Wd qw/KPt/p5jCd/0/vIzluxSEXUFayhi+FK0btoGIIa2TY3cTdE/2rdbcNx0kIMAbKsFS3 dWJUewp81XqsgaWfR8jiTLg3u3FYIHpc8s7Z6ZbqsGj1vJ/OLgVdgEsgD0mEjQMnfvT4 KFfTqmBIJfF3c+uRsHtaWesShmE4Ey3FySHOYT0pMHsQTOs9hZntsnkR5KHBpxiUzYdj mO3Nfi/2FOVd22I9Vjm0Ak/oi2cAq8Onnrl9sLM4BmUMG5dfhX+98qbmGjkp9zoDCzsU ng== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kb1258whv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 20 Oct 2022 04:15:02 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 20 Oct 2022 04:15:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 20 Oct 2022 04:15:00 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 517373F7044; Thu, 20 Oct 2022 04:14:58 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Vidya Sagar Velumuri , Subject: [PATCH 09/13] crypto/cnxk: support PDCP AAD in CPT PMD Date: Thu, 20 Oct 2022 16:44:49 +0530 Message-ID: <20221020111453.1982947-3-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020111453.1982947-1-ktejasree@marvell.com> References: <20221020111453.1982947-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Y6rKopHhGFYxf_0-etxK-fHjJx71rZ1x X-Proofpoint-ORIG-GUID: Y6rKopHhGFYxf_0-etxK-fHjJx71rZ1x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding support for PDCP AAD in 96xx crypto pmd. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 10 +-- drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 4 +- drivers/crypto/cnxk/cnxk_se.h | 86 +++++++++++------------- 3 files changed, 48 insertions(+), 52 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index e0ceaa32d5..a9c42205e6 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -27,11 +27,13 @@ cnxk_cpt_get_mlen(void) len = 2 * sizeof(uint64_t); len += ROC_SE_MAX_MAC_LEN * sizeof(uint8_t); + /* For PDCP_CHAIN passthrough alignment */ + len += 8; len += ROC_SE_OFF_CTRL_LEN + ROC_CPT_AES_CBC_IV_LEN; - len += RTE_ALIGN_CEIL((ROC_SE_SG_LIST_HDR_SIZE + - (RTE_ALIGN_CEIL(ROC_SE_MAX_SG_IN_OUT_CNT, 4) >> - 2) * ROC_SE_SG_ENTRY_SIZE), - 8); + len += RTE_ALIGN_CEIL( + (ROC_SE_SG_LIST_HDR_SIZE + + (RTE_ALIGN_CEIL(ROC_SE_MAX_SG_IN_OUT_CNT, 4) >> 2) * ROC_SE_SG_ENTRY_SIZE), + 8); return len; } diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index 2064120505..13c90444d6 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -10,8 +10,8 @@ #include "roc_api.h" -#define CNXK_CPT_MIN_HEADROOM_REQ 24 -#define CNXK_CPT_MIN_TAILROOM_REQ 102 +#define CNXK_CPT_MIN_HEADROOM_REQ 32 +#define CNXK_CPT_MIN_TAILROOM_REQ 102 /* Default command timeout in seconds */ #define DEFAULT_COMMAND_TIMEOUT 4 diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 9ce75c07e0..abb9965d3e 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -1393,12 +1393,11 @@ cpt_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens, static __rte_always_inline int cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, - struct roc_se_fc_params *params, - struct cpt_inst_s *inst) + struct roc_se_fc_params *params, struct cpt_inst_s *inst) { + uint32_t encr_data_len, auth_data_len, aad_len, passthr_len, pad_len, hdr_len; uint32_t encr_offset, auth_offset, iv_offset = 0; uint8_t *auth_iv = NULL, *cipher_iv = NULL; - uint32_t encr_data_len, auth_data_len; uint8_t pdcp_ci_alg, pdcp_auth_alg; union cpt_inst_w4 cpt_inst_w4; struct roc_se_ctx *se_ctx; @@ -1413,12 +1412,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, encr_offset = ROC_SE_ENCR_OFFSET(d_offs); auth_offset = ROC_SE_AUTH_OFFSET(d_offs); - if (auth_offset != encr_offset) { - plt_dp_err("encr_offset and auth_offset are not same"); - plt_dp_err("enc_offset: %d", encr_offset); - plt_dp_err("auth_offset: %d", auth_offset); - return -1; - } + aad_len = encr_offset - auth_offset; if (unlikely(encr_offset >> 16)) { plt_dp_err("Offset not supported"); @@ -1433,12 +1427,16 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, encr_data_len = ROC_SE_ENCR_DLEN(d_lens); auth_data_len = ROC_SE_AUTH_DLEN(d_lens); + auth_data_len -= aad_len; + + encr_offset += iv_len; + auth_offset = encr_offset - aad_len; + passthr_len = RTE_ALIGN_CEIL(auth_offset, 8); - if ((auth_data_len + mac_len) != encr_data_len) { - plt_dp_err("(auth_data_len + mac_len) != encr_data_len"); - plt_dp_err("auth_data_len: %d", auth_data_len); - plt_dp_err("encr_data_len: %d", encr_data_len); - plt_dp_err("mac_len: %d", mac_len); + if (unlikely((aad_len >> 16) || (passthr_len >> 8))) { + plt_dp_err("Length not supported"); + plt_dp_err("AAD_len: %d", aad_len); + plt_dp_err("Passthrough_len: %d", passthr_len); return -1; } @@ -1454,12 +1452,15 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, if (likely(params->cipher_iv_len)) cipher_iv = params->iv_buf; - encr_offset += iv_len; + pad_len = passthr_len - auth_offset; + hdr_len = iv_len + pad_len; if (se_ctx->auth_then_ciph) - inputlen = encr_offset + auth_data_len; + inputlen = auth_data_len; else - inputlen = encr_offset + encr_data_len; + inputlen = encr_data_len; + + inputlen += (encr_offset + pad_len); if (likely(((req_flags & ROC_SE_SINGLE_BUF_INPLACE)) && ((req_flags & ROC_SE_SINGLE_BUF_HEADROOM)))) { @@ -1468,19 +1469,18 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, /* Use Direct mode */ - offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - - ROC_SE_OFF_CTRL_LEN - iv_len); + offset_vaddr = PLT_PTR_SUB(dm_vaddr, ROC_SE_OFF_CTRL_LEN + hdr_len); /* DPTR */ inst->dptr = (uint64_t)offset_vaddr; /* RPTR should just exclude offset control word */ - inst->rptr = (uint64_t)dm_vaddr - iv_len; + inst->rptr = (uint64_t)PLT_PTR_SUB(dm_vaddr, hdr_len); cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN; *(uint64_t *)offset_vaddr = - rte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) | - ((uint64_t)(encr_offset))); + rte_cpu_to_be_64(((uint64_t)(aad_len) << 16) | + ((uint64_t)(iv_offset) << 8) | ((uint64_t)(passthr_len))); iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); @@ -1499,8 +1499,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, /* save space for IV */ offset_vaddr = m_vaddr; - m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + - RTE_ALIGN_CEIL(iv_len, 8); + m_vaddr = PLT_PTR_ADD(m_vaddr, ROC_SE_OFF_CTRL_LEN + RTE_ALIGN_CEIL(hdr_len, 8)); cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE; @@ -1519,11 +1518,11 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, /* Offset control word followed by iv */ i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr, - ROC_SE_OFF_CTRL_LEN + iv_len); + ROC_SE_OFF_CTRL_LEN + hdr_len); *(uint64_t *)offset_vaddr = - rte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) | - ((uint64_t)(encr_offset))); + rte_cpu_to_be_64(((uint64_t)(aad_len) << 16) | + ((uint64_t)(iv_offset) << 8) | ((uint64_t)(passthr_len))); iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); @@ -1532,11 +1531,10 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv); /* input data */ - size = inputlen - iv_len; + size = inputlen - hdr_len; if (size) { - i = fill_sg_comp_from_iov(gather_comp, i, - params->src_iov, 0, &size, - NULL, 0); + i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov, 0, &size, NULL, + 0); if (unlikely(size)) { plt_dp_err("Insufficient buffer space," " size %d needed", @@ -1553,29 +1551,25 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, */ i = 0; - scatter_comp = - (struct roc_se_sglist_comp *)((uint8_t *)gather_comp + - g_size_bytes); + scatter_comp = (struct roc_se_sglist_comp *)((uint8_t *)gather_comp + g_size_bytes); - if (iv_len) { + if ((hdr_len)) { i = fill_sg_comp(scatter_comp, i, - (uint64_t)offset_vaddr + - ROC_SE_OFF_CTRL_LEN, - iv_len); + (uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN, hdr_len); } /* Add output data */ - if (se_ctx->ciph_then_auth && - (req_flags & ROC_SE_VALID_MAC_BUF)) - size = inputlen - iv_len; + if (se_ctx->ciph_then_auth && (req_flags & ROC_SE_VALID_MAC_BUF)) + size = inputlen; else /* Output including mac */ - size = inputlen - iv_len + mac_len; + size = inputlen + mac_len; + + size -= hdr_len; if (size) { - i = fill_sg_comp_from_iov(scatter_comp, i, - params->dst_iov, 0, &size, - NULL, 0); + i = fill_sg_comp_from_iov(scatter_comp, i, params->dst_iov, 0, &size, NULL, + 0); if (unlikely(size)) { plt_dp_err("Insufficient buffer space," @@ -2399,7 +2393,7 @@ prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt, *flags |= ROC_SE_SINGLE_BUF_INPLACE; headroom = rte_pktmbuf_headroom(pkt); - if (likely(headroom >= 24)) + if (likely(headroom >= CNXK_CPT_MIN_HEADROOM_REQ)) *flags |= ROC_SE_SINGLE_BUF_HEADROOM; param->bufs[0].vaddr = seg_data;