From patchwork Thu Oct 20 11:14:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 118782 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D40A7A0552; Thu, 20 Oct 2022 13:15:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D93DB42D54; Thu, 20 Oct 2022 13:15:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B01CA42D45 for ; Thu, 20 Oct 2022 13:15:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29K6Q4Hq008931 for ; Thu, 20 Oct 2022 04:15:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=7yGE3OUpnmsv0+gdZ4Q+nPqKnQYqFnHNxrMD/3wwGP0=; b=KguQGwabYqw+s6mpkeS0wSdDyh6A7PSs8Z8oA01LkcMlHvsRxW/Bly2N9o1DKM+Nbn0V mNtgkglGzUu4/fbklfacdRpx2kFEVEknXvF/MsflCq+p+oJTkP1QcUTInBaYP/7mwPSm fSXl4rjQWfZ7g0LN28bP3WLHX/1qHthleUlUqX7Ka6tIDaGX3CRM1SHpACk46RYqzLro WXXoOI7Ef/RrZ1n4Q6BK0a4FuJmTpPf/JrrD0glrapcUWfOpXCI2euzgjMzi/fTLHWLF fd088q0UppbX++rgH62WD8aKL8pDsD9R7c0jz/W3sms922YdEJkx+HjGrW7xmQYIw+2b +A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3kb1258wj6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 20 Oct 2022 04:15:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 20 Oct 2022 04:15:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Oct 2022 04:15:02 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 55B063F7079; Thu, 20 Oct 2022 04:15:00 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Vidya Sagar Velumuri , Anoob Joseph , Subject: [PATCH 10/13] crypto/cnxk: acquire lock while updating antireplay Date: Thu, 20 Oct 2022 16:44:50 +0530 Message-ID: <20221020111453.1982947-4-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020111453.1982947-1-ktejasree@marvell.com> References: <20221020111453.1982947-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: xEn9y9WcjZuG_Y0EjQFeSUz7sTWtNYW4 X-Proofpoint-ORIG-GUID: xEn9y9WcjZuG_Y0EjQFeSUz7sTWtNYW4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-20_03,2022-10-20_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Acquire locks in antireplay logic to avoid race condition Signed-off-by: Vidya Sagar Velumuri --- drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c index 2a5c00eadd..04c004bc7a 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c @@ -500,6 +500,7 @@ ipsec_antireplay_check(struct cn9k_sec_session *sess, uint32_t win_sz, if (unlikely(seq == 0)) return IPSEC_ANTI_REPLAY_FAILED; + rte_spinlock_lock(&sess->ar.lock); ret = cnxk_on_anti_replay_check(seq, &sess->ar, win_sz); if (esn && !ret) { esn_low = rte_be_to_cpu_32(common_sa->seq_t.tl); @@ -510,6 +511,7 @@ ipsec_antireplay_check(struct cn9k_sec_session *sess, uint32_t win_sz, common_sa->seq_t.th = rte_cpu_to_be_32(seqh); } } + rte_spinlock_unlock(&sess->ar.lock); return ret; }