From patchwork Mon Oct 31 16:08:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 119367 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CFAAEA0540; Mon, 31 Oct 2022 17:08:49 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4DE85410F2; Mon, 31 Oct 2022 17:08:44 +0100 (CET) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by mails.dpdk.org (Postfix) with ESMTP id 3AD2040151; Mon, 31 Oct 2022 17:08:41 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=N014IjoOvLI13btTcWBluZoy0c+Yqr6I2NodAS1XjG8JBQUGpg6YL9D/KtKapLey84kNHQZAIEA+EaJSrx+ob4SAYYzlBa3FSU97IAeXsYIsejfTy9c7tNibuVnsyVr5yvN/sfbaglVuXnODAze0VdFCCOOVdPYW1JrXvXAbTNa/mTviECVcfdgYNjIAwE3LT0062JMQweO/Emz6MaTcTdgXyeibmjf45lhVO5whWB2WZIJLDVxNh16qkyjuRyxJpyRGx409ydi0zfwkgTfaElyMB9nl/GCYLenErdiME8XBI4FInE4ffcdlDJVwzLi36z1FGLesGeLHCVlIupm9+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vCP+cQ5BkgEEk4BT0OfU5sX6nIBRKj5sPRSn5o0DvLA=; b=CY9oCy0nTRHR9VZuEjkdqLk5ud/0aO9rb6hbVEkp3c6APYAz1clw0Ig8ESXo4YHDsE+Hcwx0X9ooiYTWC9vqAeTRFdZ4ESfoI/jkNp/yUdiMndmT3jpUucuJ8zL3DVn5Tc3HEoSADu7iwUSHfEdOd18f6TZCyBane1Y7zEh/dHdHy/FlRfEdxF4BCVRN2cKm0cNf8Hog+AysDytdFVk4m814OPyhsF7xtkZiQ0TEXIEZFlkCIx34lUpBMhom+u9F3YaXEMOhO2jqju6mMh1Ta0YVarufcuBlmlIMBIfr42fYHexLGwY9A1CVnLMa5yaAHbquwY/COml4Q4jW5FN6xw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vCP+cQ5BkgEEk4BT0OfU5sX6nIBRKj5sPRSn5o0DvLA=; b=I7sgxKwjqeGY97tnDOosxAG/35peY1Q7CQmMoBWifrTqtTfJ93/M3eEDG6pr0Z+4dhl9RAp8u3H/rfF2C8NHM9dz8/Z2HEO9STSPkJZacLBsqQmJfbeW/MRM3H+PjEfvanRhLWcUjIUXS+AyDMvy9fi8ktvNhEEF0zjwFrj7v2OAc25F9XofsTZcP0wS8+Mfn3ICVs4YKcnrGY+mQoOPn6QTkw2ybUUxbMfbr0Xw4pvkz2Hra6BChipwZ2anWRlwNENU50tqfXjMBIlbu3UcYge4uTdlZIRVbuUb38GPBbELIkDdqiNyIRZ/zCUCJU+VjD9MWV2VxbjmGpru7xHA8A== Received: from BN9PR03CA0937.namprd03.prod.outlook.com (2603:10b6:408:108::12) by MN2PR12MB4109.namprd12.prod.outlook.com (2603:10b6:208:1d9::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.16; Mon, 31 Oct 2022 16:08:39 +0000 Received: from BN8NAM11FT034.eop-nam11.prod.protection.outlook.com (2603:10b6:408:108:cafe::7d) by BN9PR03CA0937.outlook.office365.com (2603:10b6:408:108::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.19 via Frontend Transport; Mon, 31 Oct 2022 16:08:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BN8NAM11FT034.mail.protection.outlook.com (10.13.176.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5769.14 via Frontend Transport; Mon, 31 Oct 2022 16:08:38 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Mon, 31 Oct 2022 09:08:31 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 31 Oct 2022 09:08:31 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29 via Frontend Transport; Mon, 31 Oct 2022 09:08:29 -0700 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , , Subject: [PATCH 1/5] net/mlx5: fix race condition in counter pool resizing Date: Mon, 31 Oct 2022 18:08:20 +0200 Message-ID: <20221031160824.330200-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221031160824.330200-1-michaelba@nvidia.com> References: <20221031160824.330200-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT034:EE_|MN2PR12MB4109:EE_ X-MS-Office365-Filtering-Correlation-Id: 6adcbac8-55dc-4b7c-e893-08dabb5a2c46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: K/tRsyRs8hyR689km1/3e4pmO069ZSkFXiHatKU+IseTLDHSYRT7vioeMCyEmHZubpGEf/A+0mif/BqAh+OKZ4wtTyHm4b1DfgTMKb4w3juTlbFAkagn+oMqXU8rSVbJu+xI8ea0uras3AS32p8tHuFZGpqBrcQFHgaZnZ+8GyHYi+rjFafMOOFrerZ5YxRKACmBu+ymU++dDopjJPM2Nd6sycHcMO9scI6LCSHjvPGP27yemsgBbc6EvlRLUJgxWt7FSxxmnpNL0u7Kkq+qqcbMkfVMmTnWxlYOrw1TdaANETOzaiaMo1md0m5X2TKkY6+JSDdLCsh95n2lxgf0x92aYKAQg7oXKejNcO3S5whIpSOyg0CMwp4AQXOTLkff3wLwLdaRLbMF2rMGHOx/CNyxibZx5aEZXrEHjee4I36dQoaOaIYpZzGsTlG4Lu6dsjGNlf7Ia7k1YKRdjkCFmd2wGOf5rOJZ6gp6FyZZFsBN6S9c5JZGTnrh/A9FY8EJRGY8z+Ww5lXMI+WUJnDdO3cSHDf1fQoXoLTpdtNbCs1t4oXAT+MH91ZQsr8L9HOW/J4n7r+mUlOy+YRVf5+T98SjuNKT2UkZC5zxQkpIG9UA8Qao+ZgKqwxLthuQEft++S61em454+7tUP2xhMUNQT/wKvrY8OH0Lh1IS4+sOMRUCS2WgvRs9Q4jY8lNyi7LuMmJ5GwECD6qZzT74EgO92zDilMnR9qtBsrrggbk0NqDiucHW3/WD2Q0Y69aZwrhDA2dcRpfQi7tTdYdqecqDA== X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199015)(40470700004)(46966006)(36840700001)(6666004)(6286002)(478600001)(26005)(316002)(54906003)(6916009)(7696005)(82310400005)(55016003)(36860700001)(7636003)(47076005)(40460700003)(40480700001)(336012)(356005)(36756003)(2616005)(82740400003)(1076003)(186003)(83380400001)(86362001)(426003)(2906002)(4326008)(70586007)(8676002)(70206006)(41300700001)(30864003)(450100002)(8936002)(5660300002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2022 16:08:38.8766 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6adcbac8-55dc-4b7c-e893-08dabb5a2c46 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4109 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Counter management structure has array of counter pools. This array is invalid in management structure initialization and grows on demand. The resizing include: 1. Allocate memory for the new size. 2. Copy the existing data to the new memory. 3. Move the pointer to the new memory. 4. Free the old memory. The third step can be performed before for this function, and compiler may do that, but another thread might read the pointer before coping and read invalid data or even crash. This patch allocates memory for this array once in management structure initialization and limit the counters number by 16M. Fixes: 3aa279157fa0 ("net/mlx5: synchronize flow counter pool creation") Cc: suanmingm@nvidia.com Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5.c | 28 +++++++++++++--- drivers/net/mlx5/mlx5.h | 7 ++-- drivers/net/mlx5/mlx5_flow.c | 24 +++++++------- drivers/net/mlx5/mlx5_flow_dv.c | 53 +++++------------------------- drivers/net/mlx5/mlx5_flow_verbs.c | 23 +++---------- 5 files changed, 52 insertions(+), 83 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 78234b116c..b85a56ec24 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -561,18 +561,34 @@ mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) * * @param[in] sh * Pointer to mlx5_dev_ctx_shared object to free + * + * @return + * 0 on success, otherwise negative errno value and rte_errno is set. */ -static void +static int mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) { int i, j; if (sh->config.dv_flow_en < 2) { + void *pools; + + pools = mlx5_malloc(MLX5_MEM_ZERO, + sizeof(struct mlx5_flow_counter_pool *) * + MLX5_COUNTER_POOLS_MAX_NUM, + 0, SOCKET_ID_ANY); + if (!pools) { + DRV_LOG(ERR, + "Counter management allocation was failed."); + rte_errno = ENOMEM; + return -rte_errno; + } memset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng)); TAILQ_INIT(&sh->sws_cmng.flow_counters); sh->sws_cmng.min_id = MLX5_CNT_BATCH_OFFSET; sh->sws_cmng.max_id = -1; sh->sws_cmng.last_pool_idx = POOL_IDX_INVALID; + sh->sws_cmng.pools = pools; rte_spinlock_init(&sh->sws_cmng.pool_update_sl); for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) { TAILQ_INIT(&sh->sws_cmng.counters[i]); @@ -598,6 +614,7 @@ mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) sh->hws_max_log_bulk_sz = log_dcs; sh->hws_max_nb_counters = max_nb_cnts; } + return 0; } /** @@ -655,8 +672,7 @@ mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh) claim_zero (mlx5_flow_os_destroy_flow_action (cnt->action)); - if (fallback && MLX5_POOL_GET_CNT - (pool, j)->dcs_when_free) + if (fallback && cnt->dcs_when_free) claim_zero(mlx5_devx_cmd_destroy (cnt->dcs_when_free)); } @@ -1572,8 +1588,12 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, if (err) goto error; } + err = mlx5_flow_counters_mng_init(sh); + if (err) { + DRV_LOG(ERR, "Fail to initialize counters manage."); + goto error; + } mlx5_flow_aging_init(sh); - mlx5_flow_counters_mng_init(sh); mlx5_flow_ipool_create(sh); /* Add context to the global device list. */ LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next); diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index c9fcb71b69..cbe2d88b9e 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -386,11 +386,10 @@ struct mlx5_hw_q { } __rte_cache_aligned; - - +#define MLX5_COUNTER_POOLS_MAX_NUM (1 << 15) #define MLX5_COUNTERS_PER_POOL 512 #define MLX5_MAX_PENDING_QUERIES 4 -#define MLX5_CNT_CONTAINER_RESIZE 64 +#define MLX5_CNT_MR_ALLOC_BULK 64 #define MLX5_CNT_SHARED_OFFSET 0x80000000 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ MLX5_CNT_BATCH_OFFSET) @@ -549,7 +548,6 @@ TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); /* Counter global management structure. */ struct mlx5_flow_counter_mng { volatile uint16_t n_valid; /* Number of valid pools. */ - uint16_t n; /* Number of pools. */ uint16_t last_pool_idx; /* Last used pool index */ int min_id; /* The minimum counter ID in the pools. */ int max_id; /* The maximum counter ID in the pools. */ @@ -621,6 +619,7 @@ struct mlx5_aso_age_action { }; #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 +#define MLX5_ASO_AGE_CONTAINER_RESIZE 64 struct mlx5_aso_age_pool { struct mlx5_devx_obj *flow_hit_aso_obj; diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 8e7d649d15..e25154199f 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -9063,7 +9063,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) { struct mlx5_counter_stats_mem_mng *mem_mng; volatile struct flow_counter_stats *raw_data; - int raws_n = MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES; + int raws_n = MLX5_CNT_MR_ALLOC_BULK + MLX5_MAX_PENDING_QUERIES; int size = (sizeof(struct flow_counter_stats) * MLX5_COUNTERS_PER_POOL + sizeof(struct mlx5_counter_stats_raw)) * raws_n + @@ -9101,7 +9101,7 @@ mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) } for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, - mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE + i, + mem_mng->raws + MLX5_CNT_MR_ALLOC_BULK + i, next); LIST_INSERT_HEAD(&sh->sws_cmng.mem_mngs, mem_mng, next); sh->sws_cmng.mem_mng = mem_mng; @@ -9125,14 +9125,13 @@ mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, { struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; /* Resize statistic memory once used out. */ - if (!(pool->index % MLX5_CNT_CONTAINER_RESIZE) && + if (!(pool->index % MLX5_CNT_MR_ALLOC_BULK) && mlx5_flow_create_counter_stat_mem_mng(sh)) { DRV_LOG(ERR, "Cannot resize counter stat mem."); return -1; } rte_spinlock_lock(&pool->sl); - pool->raw = cmng->mem_mng->raws + pool->index % - MLX5_CNT_CONTAINER_RESIZE; + pool->raw = cmng->mem_mng->raws + pool->index % MLX5_CNT_MR_ALLOC_BULK; rte_spinlock_unlock(&pool->sl); pool->raw_hw = NULL; return 0; @@ -9174,13 +9173,13 @@ void mlx5_flow_query_alarm(void *arg) { struct mlx5_dev_ctx_shared *sh = arg; - int ret; - uint16_t pool_index = sh->sws_cmng.pool_index; struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; + uint16_t pool_index = cmng->pool_index; struct mlx5_flow_counter_pool *pool; uint16_t n_valid; + int ret; - if (sh->sws_cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) + if (cmng->pending_queries >= MLX5_MAX_PENDING_QUERIES) goto set_alarm; rte_spinlock_lock(&cmng->pool_update_sl); pool = cmng->pools[pool_index]; @@ -9192,8 +9191,7 @@ mlx5_flow_query_alarm(void *arg) if (pool->raw_hw) /* There is a pool query in progress. */ goto set_alarm; - pool->raw_hw = - LIST_FIRST(&sh->sws_cmng.free_stat_raws); + pool->raw_hw = LIST_FIRST(&cmng->free_stat_raws); if (!pool->raw_hw) /* No free counter statistics raw memory. */ goto set_alarm; @@ -9219,12 +9217,12 @@ mlx5_flow_query_alarm(void *arg) goto set_alarm; } LIST_REMOVE(pool->raw_hw, next); - sh->sws_cmng.pending_queries++; + cmng->pending_queries++; pool_index++; if (pool_index >= n_valid) pool_index = 0; set_alarm: - sh->sws_cmng.pool_index = pool_index; + cmng->pool_index = pool_index; mlx5_set_query_alarm(sh); } @@ -9755,7 +9753,7 @@ mlx5_flow_dev_dump_sh_all(struct rte_eth_dev *dev, } /* get counter */ - MLX5_ASSERT(cmng->n_valid <= cmng->n); + MLX5_ASSERT(cmng->n_valid <= MLX5_COUNTER_POOLS_MAX_NUM); max = MLX5_COUNTERS_PER_POOL * cmng->n_valid; for (j = 1; j <= max; j++) { action = NULL; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 1e52278191..e77cbb862b 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -6091,7 +6091,7 @@ flow_dv_counter_get_by_idx(struct rte_eth_dev *dev, /* Decrease to original index and clear shared bit. */ idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1); - MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n); + MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < MLX5_COUNTER_POOLS_MAX_NUM); pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL]; MLX5_ASSERT(pool); if (ppool) @@ -6167,39 +6167,6 @@ flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id) return pool; } -/** - * Resize a counter container. - * - * @param[in] dev - * Pointer to the Ethernet device structure. - * - * @return - * 0 on success, otherwise negative errno value and rte_errno is set. - */ -static int -flow_dv_container_resize(struct rte_eth_dev *dev) -{ - struct mlx5_priv *priv = dev->data->dev_private; - struct mlx5_flow_counter_mng *cmng = &priv->sh->sws_cmng; - void *old_pools = cmng->pools; - uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE; - uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize; - void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY); - - if (!pools) { - rte_errno = ENOMEM; - return -ENOMEM; - } - if (old_pools) - memcpy(pools, old_pools, cmng->n * - sizeof(struct mlx5_flow_counter_pool *)); - cmng->n = resize; - cmng->pools = pools; - if (old_pools) - mlx5_free(old_pools); - return 0; -} - /** * Query a devx flow counter. * @@ -6251,8 +6218,6 @@ _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts, * The devX counter handle. * @param[in] age * Whether the pool is for counter that was allocated for aging. - * @param[in/out] cont_cur - * Pointer to the container pointer, it will be update in pool resize. * * @return * The pool container pointer on success, NULL otherwise and rte_errno is set. @@ -6264,9 +6229,14 @@ flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs, struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_flow_counter_pool *pool; struct mlx5_flow_counter_mng *cmng = &priv->sh->sws_cmng; - bool fallback = priv->sh->sws_cmng.counter_fallback; + bool fallback = cmng->counter_fallback; uint32_t size = sizeof(*pool); + if (cmng->n_valid == MLX5_COUNTER_POOLS_MAX_NUM) { + DRV_LOG(ERR, "All counter is in used, try again later."); + rte_errno = EAGAIN; + return NULL; + } size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE; size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE); pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY); @@ -6285,11 +6255,6 @@ flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs, pool->time_of_last_age_check = MLX5_CURR_TIME_SEC; rte_spinlock_lock(&cmng->pool_update_sl); pool->index = cmng->n_valid; - if (pool->index == cmng->n && flow_dv_container_resize(dev)) { - mlx5_free(pool); - rte_spinlock_unlock(&cmng->pool_update_sl); - return NULL; - } cmng->pools[pool->index] = pool; cmng->n_valid++; if (unlikely(fallback)) { @@ -12511,7 +12476,7 @@ flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx) } /** - * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools. + * Resize the ASO age pools array by MLX5_ASO_AGE_CONTAINER_RESIZE pools. * * @param[in] dev * Pointer to the Ethernet device structure. @@ -12525,7 +12490,7 @@ flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev) struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; void *old_pools = mng->pools; - uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE; + uint32_t resize = mng->n + MLX5_ASO_AGE_CONTAINER_RESIZE; uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize; void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY); diff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c index 81a33ddf09..4bca685674 100644 --- a/drivers/net/mlx5/mlx5_flow_verbs.c +++ b/drivers/net/mlx5/mlx5_flow_verbs.c @@ -232,27 +232,14 @@ flow_verbs_counter_new(struct rte_eth_dev *dev, uint32_t id __rte_unused) break; } if (!cnt) { - struct mlx5_flow_counter_pool **pools; uint32_t size; - if (n_valid == cmng->n) { - /* Resize the container pool array. */ - size = sizeof(struct mlx5_flow_counter_pool *) * - (n_valid + MLX5_CNT_CONTAINER_RESIZE); - pools = mlx5_malloc(MLX5_MEM_ZERO, size, 0, - SOCKET_ID_ANY); - if (!pools) - return 0; - if (n_valid) { - memcpy(pools, cmng->pools, - sizeof(struct mlx5_flow_counter_pool *) * - n_valid); - mlx5_free(cmng->pools); - } - cmng->pools = pools; - cmng->n += MLX5_CNT_CONTAINER_RESIZE; + if (n_valid == MLX5_COUNTER_POOLS_MAX_NUM) { + DRV_LOG(ERR, "All counter is in used, try again later."); + rte_errno = EAGAIN; + return 0; } - /* Allocate memory for new pool*/ + /* Allocate memory for new pool */ size = sizeof(*pool) + sizeof(*cnt) * MLX5_COUNTERS_PER_POOL; pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY); if (!pool)