From patchwork Mon Jan 16 09:39:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 122085 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D4E5A423EE; Mon, 16 Jan 2023 10:40:58 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 700EA42BB1; Mon, 16 Jan 2023 10:40:56 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B1A6342BB1 for ; Mon, 16 Jan 2023 10:40:54 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30G63aaV000602 for ; Mon, 16 Jan 2023 01:40:53 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=KM9OzX+tQ8cVcqJJ/boowUfohCNZ7kwClRfPu695QI0=; b=KY81d5q4TMNrAt4rBi5IdTqvkxdF9ZIa1ecuzvpbyzk+qpPUDwXYdT5kK9KkFRVaVX32 ORR/FmmsjPaVbeoZuAr3NRC/H+qK818ojRZjUO9ju4+o0mnY1SyOLWxPf+FjtvRpqiXt ZVW/+gi4Clb2psX0//+Q/l/VGU9tEJmRn6TrSmeCvd1WtlN7MUqzFLylFRNiyXcGsoHY T61jiI8y8NvHvI5PWgwQRRO5U1I9OyT6HD7e/lphBLghaABGWIX48+KVlUdz8bGR0yp6 vKRc/61S83ITmat/krItlp3Uf81WnfuTofNsNv2hsz2UEnez5mqJL9T9Na/X03jli04M BA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3n3tmvkuj6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 16 Jan 2023 01:40:53 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 16 Jan 2023 01:40:51 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Mon, 16 Jan 2023 01:40:51 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 86B8C3F7058; Mon, 16 Jan 2023 01:40:49 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH 2/9] common/cnxk: enable CQ late BP with valid CPT BPID Date: Mon, 16 Jan 2023 15:09:47 +0530 Message-ID: <20230116093954.172938-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230116093954.172938-1-ndabilpuram@marvell.com> References: <20230116093954.172938-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: jSMGwl_gcaO8zCAbwKeyIIDJ8hO36bdm X-Proofpoint-GUID: jSMGwl_gcaO8zCAbwKeyIIDJ8hO36bdm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.923,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-16_08,2023-01-13_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao When FC enable requested for CPT, mbox returns allocated BPID. While configuring CQ consider this value to enable late back pressure. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_fc.c | 2 ++ drivers/common/cnxk/roc_nix_priv.h | 1 + drivers/common/cnxk/roc_nix_queue.c | 19 +++++++++++++------ 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index 569fe8dc48..784e6e5416 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -83,6 +83,7 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable) rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) goto exit; + nix->cpt_lbpid = rsp->chan_bpid[0] & 0x1FF; } else { req = mbox_alloc_msg_nix_cpt_bp_disable(mbox); if (req == NULL) @@ -94,6 +95,7 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable) rc = mbox_process_msg(mbox, (void *)&rsp); if (rc) goto exit; + nix->cpt_lbpid = 0; } exit: diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h index 0a9461c856..7d2e3626a3 100644 --- a/drivers/common/cnxk/roc_nix_priv.h +++ b/drivers/common/cnxk/roc_nix_priv.h @@ -205,6 +205,7 @@ struct nix { uint16_t nb_cpt_lf; uint16_t outb_se_ring_cnt; uint16_t outb_se_ring_base; + uint16_t cpt_lbpid; bool need_meta_aura; /* Mode provided by driver */ bool inb_inl_dev; diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 20a1e7d4d8..385f1ba04e 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -798,7 +798,7 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) struct mbox *mbox = (&nix->dev)->mbox; volatile struct nix_cq_ctx_s *cq_ctx; uint16_t drop_thresh = NIX_CQ_THRESH_LEVEL; - uint16_t cpt_lbpid = nix->bpid[0]; + uint16_t cpt_lbpid = nix->cpt_lbpid; enum nix_q_size qsize; size_t desc_sz; int rc; @@ -860,11 +860,14 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq) if (roc_model_is_cn10kb() && roc_nix_inl_inb_is_enabled(roc_nix)) { cq_ctx->cq_err_int_ena |= BIT(NIX_CQERRINT_CPT_DROP); cq_ctx->cpt_drop_err_en = 1; - cq_ctx->lbp_ena = 1; - cq_ctx->lbpid_low = cpt_lbpid & 0x7; - cq_ctx->lbpid_med = (cpt_lbpid >> 3) & 0x7; - cq_ctx->lbpid_high = (cpt_lbpid >> 6) & 0x7; - cq_ctx->lbp_frac = NIX_CQ_LPB_THRESH_FRAC; + /* Enable Late BP only when non zero CPT BPID */ + if (cpt_lbpid) { + cq_ctx->lbp_ena = 1; + cq_ctx->lbpid_low = cpt_lbpid & 0x7; + cq_ctx->lbpid_med = (cpt_lbpid >> 3) & 0x7; + cq_ctx->lbpid_high = (cpt_lbpid >> 6) & 0x7; + cq_ctx->lbp_frac = NIX_CQ_LPB_THRESH_FRAC; + } drop_thresh = NIX_CQ_SEC_THRESH_LEVEL; } @@ -959,6 +962,10 @@ roc_nix_cq_fini(struct roc_nix_cq *cq) aq->cq.bp_ena = 0; aq->cq_mask.ena = ~aq->cq_mask.ena; aq->cq_mask.bp_ena = ~aq->cq_mask.bp_ena; + if (roc_model_is_cn10kb() && roc_nix_inl_inb_is_enabled(cq->roc_nix)) { + aq->cq.lbp_ena = 0; + aq->cq_mask.lbp_ena = ~aq->cq_mask.lbp_ena; + } } rc = mbox_process(mbox);