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Mon, 20 Feb 2023 23:08:14 -0800 From: Michael Baum To: CC: Matan Azrad , Akhil Goyal , "Thomas Monjalon" Subject: [PATCH v3 7/8] common/mlx5: add LZ4 capabilities check Date: Tue, 21 Feb 2023 09:07:55 +0200 Message-ID: <20230221070756.3070819-8-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230221070756.3070819-1-michaelba@nvidia.com> References: <20230202162537.1067595-1-michaelba@nvidia.com> <20230221070756.3070819-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT083:EE_|CO6PR12MB5490:EE_ X-MS-Office365-Filtering-Correlation-Id: 447945f2-8387-4b7b-0c86-08db13da717d X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YiZeAsL4bwQu8s/6nG4msudHkMN8UqU+wSWVZLbCfgw4KFY3okfVwW2OCAs69ZR/LPqBAqFIkRjL8A9baGYcJzZ677gimL+LjpVCJRbjJPzbbSCKW1LEf4SzDLYi+vFNJCrkW2LVnc2kbz3rG9UH5mmIN2l/7gedIR3WocUQTtf1BDtM13BZuDTmFNYHW7MJcjiooCiFip3Vumj4n+5f70ew+ZeEnpOyRWGUa+BxAdoMyHEqq5PhSDy41neKqvWvcJY5FiqC8X3YBuVcyewL5+BPCdS3GdariKwpdwsA+fpXcgOM1hgpobz+i9DpiAr+Rqs/BH8ORwKQuM4ZGXRBeE1EofgJOKVv2pPFUdBoj8Q1O26IQZwRbkwyYmXpwozlaNrzePsv5d62up96hFLAGRDaamWTqk3M+MqACno3bv3RmfqsNVHnuoFSfuRHS96xN76qKwOWydxXuPBdp9IUeaTmRt5bOuh9ykw9sZ0Smxf74bABoAYB6mIiOoERFMtxoj9fsGy1tz+ekFmvfwvBcOP/G5P/ccuGVRya1aiDWjJbDbWoYDhgwuRvKWCm4YhjZ4aVWjYvIB0tp+yjofsxCYbJLxOUB1zunNflSmH4gCptBWP21D+0osC/Cfw3GFDAUgfhffT/jAfPRnIPmoLdNIEwlfRznp9zTLoBS9H4rnQhmU5CVURyAzC2uZ57rUjBm9ihvmzW1pvlg3ylW3z7WQ== X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++ drivers/common/mlx5/mlx5_prm.h | 16 ++++++++++++++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index b801b05872..bd0e1c6398 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -998,6 +998,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, log_compress_mmo_size); attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, log_decompress_mmo_size); + attr->decomp_lz4_data_only_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_lz4_data_only_v2); + attr->decomp_lz4_no_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_lz4_no_checksum_v2); + attr->decomp_lz4_checksum_en = MLX5_GET(cmd_hca_cap, hcattr, + decompress_lz4_checksum_v2); attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, mini_cqe_resp_flow_tag); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 045ff404e9..96c4c1a819 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -271,6 +271,9 @@ struct mlx5_hca_attr { uint32_t log_max_mmo_dma:5; uint32_t log_max_mmo_compress:5; uint32_t log_max_mmo_decompress:5; + uint32_t decomp_lz4_data_only_en:1; + uint32_t decomp_lz4_no_checksum_en:1; + uint32_t decomp_lz4_checksum_en:1; uint32_t umr_modify_entity_size_disabled:1; uint32_t umr_indirect_mkey_disabled:1; uint32_t log_min_stride_wqe_sz:5; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index b33c55c257..75af636f59 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -584,9 +584,19 @@ struct mlx5_rdma_write_wqe { #define MLX5_OPC_MOD_MMO_DECOMP 0x3u #define MLX5_OPC_MOD_MMO_DMA 0x1u +#define WQE_GGA_DECOMP_DEFLATE 0x0u +#define WQE_GGA_DECOMP_LZ4 0x2u + +#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITHOUT_CHECKSUM 0x1u +#define MLX5_GGA_DECOMP_LZ4_BLOCK_WITH_CHECKSUM 0x2u + #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u +#define WQE_GGA_DECOMP_PARAMS_OFFSET 20u +#define WQE_GGA_DECOMP_TYPE_OFFSET 8u +#define WQE_GGA_DECOMP_BLOCK_INDEPENDENT_OFFSET 22u + #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u @@ -605,7 +615,7 @@ struct mlx5_gga_wqe { uint32_t opcode; uint32_t sq_ds; uint32_t flags; - uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ + uint32_t gga_ctrl1; uint32_t gga_ctrl2; uint32_t opaque_lkey; uint64_t opaque_vaddr; @@ -1438,7 +1448,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_dma_mmo_size[0x5]; u8 reserved_at_70[0x3]; u8 log_compress_mmo_size[0x5]; - u8 reserved_at_78[0x3]; + u8 decompress_lz4_data_only_v2[0x1]; + u8 decompress_lz4_no_checksum_v2[0x1]; + u8 decompress_lz4_checksum_v2[0x1]; u8 log_decompress_mmo_size[0x5]; u8 log_max_srq_sz[0x8]; u8 log_max_qp_sz[0x8];