From patchwork Fri Feb 24 09:40:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 124511 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3BE9E41D5F; Fri, 24 Feb 2023 10:40:55 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 43168427F5; Fri, 24 Feb 2023 10:40:32 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A8A0E41151 for ; Fri, 24 Feb 2023 10:40:29 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31O6o4W9001318 for ; Fri, 24 Feb 2023 01:40:29 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=UsHqTZtUJCX7pJCUY0s6C1wnWwMa9qOc670Ut8TWQD8=; b=VDNCGluebZzOe3NA3M9b2LYXrELMcXtWqz9HERsVCpZrVb3ag2duf7MHSJoTcd9HrFJf FTo8rmMI1yKZrvzfBv7idhBlYGsly49mTfmkWX/y1JgVQmGqgqzoLRKQKnBY5HLuepDp EfevozlTubmBBp034625nfXwNBEc69+WX5GN1xRDuIXZ2FEsV7uoOr3eeXI0mzWR3t8q tJtjIIkxQaudhVQ8SuEjXlrTOAVqfdaumGs2hECtHd85XYBJqtQQCLQJmgkUdqa3vJp0 ExHJC9jcJ9XJesg9k/bnLC58zzCHZPgUPx960uIhnBA+ZJ3qzJuHB1iVdv5kCzuurXdC dw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3nxfkwb2gx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 24 Feb 2023 01:40:28 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 24 Feb 2023 01:40:26 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 24 Feb 2023 01:40:26 -0800 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 577B35B692C; Fri, 24 Feb 2023 01:40:25 -0800 (PST) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Gowrishankar Muthukrishnan , Subject: [PATCH v2 05/11] crypto/cnxk: set ctx for AE Date: Fri, 24 Feb 2023 15:10:08 +0530 Message-ID: <20230224094014.3246764-6-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230224094014.3246764-1-ktejasree@marvell.com> References: <20230224094014.3246764-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Gf-hIGAgUY3RUCC_4fEXah9gIMe62e04 X-Proofpoint-ORIG-GUID: Gf-hIGAgUY3RUCC_4fEXah9gIMe62e04 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-24_05,2023-02-23_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Set ctx_val to 1 for asymmetric ops. Signed-off-by: Tejasree Kondoj --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 18 ++++--------- drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 16 +++-------- drivers/crypto/cnxk/cnxk_ae.h | 21 +++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 33 ++++++++++++++++------- 4 files changed, 53 insertions(+), 35 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index 92f7002db9..d1a43eaf13 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -158,10 +158,8 @@ cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[], struct if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { asym_op = op->asym; - ae_sess = (struct cnxk_ae_sess *) - asym_op->session->sess_private_data; - ret = cnxk_ae_enqueue(qp, op, infl_req, &inst[0], - ae_sess); + ae_sess = (struct cnxk_ae_sess *)asym_op->session; + ret = cnxk_ae_enqueue(qp, op, infl_req, &inst[0], ae_sess); if (unlikely(ret)) return 0; w7 = ae_sess->cpt_inst_w7; @@ -330,10 +328,9 @@ cn10k_cpt_crypto_adapter_ev_mdata_set(struct rte_cryptodev *dev __rte_unused, vo return -EINVAL; } else if (op_type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { if (sess_type == RTE_CRYPTO_OP_WITH_SESSION) { - struct rte_cryptodev_asym_session *asym_sess = sess; struct cnxk_ae_sess *priv; - priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data; + priv = (struct cnxk_ae_sess *)sess; priv->qp = qp; priv->cpt_inst_w2 = w2; } else @@ -381,11 +378,9 @@ cn10k_ca_meta_info_extract(struct rte_crypto_op *op, struct cnxk_cpt_qp **qp, ui } } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { - struct rte_cryptodev_asym_session *asym_sess; struct cnxk_ae_sess *priv; - asym_sess = op->asym->session; - priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data; + priv = (struct cnxk_ae_sess *)op->asym->session; *qp = priv->qp; *w2 = priv->cpt_inst_w2; } else @@ -890,10 +885,7 @@ cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, } else if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { struct rte_crypto_asym_op *op = cop->asym; uintptr_t *mdata = infl_req->mdata; - struct cnxk_ae_sess *sess; - - sess = (struct cnxk_ae_sess *) - op->session->sess_private_data; + struct cnxk_ae_sess *sess = (struct cnxk_ae_sess *)op->session; cnxk_ae_post_process(cop, sess, (uint8_t *)mdata[0]); } diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c index 11541b6ab9..34d40b07d4 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c @@ -105,13 +105,10 @@ cn9k_cpt_inst_prep(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op, inst->w7.u64 = sess->cpt_inst_w7; } } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { - struct rte_crypto_asym_op *asym_op; struct cnxk_ae_sess *sess; if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { - asym_op = op->asym; - sess = (struct cnxk_ae_sess *) - asym_op->session->sess_private_data; + sess = (struct cnxk_ae_sess *)op->asym->session; ret = cnxk_ae_enqueue(qp, op, infl_req, inst, sess); inst->w7.u64 = sess->cpt_inst_w7; } else { @@ -345,7 +342,7 @@ cn9k_cpt_crypto_adapter_ev_mdata_set(struct rte_cryptodev *dev __rte_unused, struct rte_cryptodev_asym_session *asym_sess = sess; struct cnxk_ae_sess *priv; - priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data; + priv = (struct cnxk_ae_sess *)asym_sess; priv->qp = qp; priv->cpt_inst_w2 = w2; } else @@ -393,11 +390,9 @@ cn9k_ca_meta_info_extract(struct rte_crypto_op *op, } } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) { - struct rte_cryptodev_asym_session *asym_sess; struct cnxk_ae_sess *priv; - asym_sess = op->asym->session; - priv = (struct cnxk_ae_sess *)asym_sess->sess_private_data; + priv = (struct cnxk_ae_sess *)op->asym->session; *qp = priv->qp; inst->w2.u64 = priv->cpt_inst_w2; } else @@ -609,10 +604,7 @@ cn9k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp, struct rte_crypto_op *cop, } else if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) { struct rte_crypto_asym_op *op = cop->asym; uintptr_t *mdata = infl_req->mdata; - struct cnxk_ae_sess *sess; - - sess = (struct cnxk_ae_sess *) - op->session->sess_private_data; + struct cnxk_ae_sess *sess = (struct cnxk_ae_sess *)op->session; cnxk_ae_post_process(cop, sess, (uint8_t *)mdata[0]); } diff --git a/drivers/crypto/cnxk/cnxk_ae.h b/drivers/crypto/cnxk/cnxk_ae.h index 698c10129e..b7c13a9e01 100644 --- a/drivers/crypto/cnxk/cnxk_ae.h +++ b/drivers/crypto/cnxk/cnxk_ae.h @@ -13,7 +13,10 @@ #include "cnxk_cryptodev_ops.h" +#define ASYM_SESS_SIZE sizeof(struct rte_cryptodev_asym_session) + struct cnxk_ae_sess { + uint8_t rte_sess[ASYM_SESS_SIZE]; enum rte_crypto_asym_xform_type xfrm_type; union { struct rte_crypto_rsa_xform rsa_ctx; @@ -25,6 +28,24 @@ struct cnxk_ae_sess { uint64_t cpt_inst_w7; uint64_t cpt_inst_w2; struct cnxk_cpt_qp *qp; + struct roc_cpt_lf *lf; + struct hw_ctx_s { + union { + struct { + uint64_t rsvd : 48; + + uint64_t ctx_push_size : 7; + uint64_t rsvd1 : 1; + + uint64_t ctx_hdr_size : 2; + uint64_t aop_valid : 1; + uint64_t rsvd2 : 1; + uint64_t ctx_size : 4; + } s; + uint64_t u64; + } w0; + uint8_t rsvd[256]; + } hw_ctx __plt_aligned(ROC_ALIGN); }; static __rte_always_inline void diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 27f2846f74..f03646fe1a 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -760,14 +760,14 @@ cnxk_ae_session_size_get(struct rte_cryptodev *dev __rte_unused) } void -cnxk_ae_session_clear(struct rte_cryptodev *dev, - struct rte_cryptodev_asym_session *sess) +cnxk_ae_session_clear(struct rte_cryptodev *dev, struct rte_cryptodev_asym_session *sess) { - struct cnxk_ae_sess *priv; + struct cnxk_ae_sess *priv = (struct cnxk_ae_sess *)sess; - priv = (struct cnxk_ae_sess *) sess->sess_private_data; - if (priv == NULL) - return; + /* Trigger CTX flush + invalidate to remove from CTX_CACHE */ + roc_cpt_lf_ctx_flush(priv->lf, &priv->hw_ctx, true); + + plt_delay_ms(1); /* Free resources allocated in session_cfg */ cnxk_ae_free_session_parameters(priv); @@ -777,23 +777,36 @@ cnxk_ae_session_clear(struct rte_cryptodev *dev, } int -cnxk_ae_session_cfg(struct rte_cryptodev *dev, - struct rte_crypto_asym_xform *xform, +cnxk_ae_session_cfg(struct rte_cryptodev *dev, struct rte_crypto_asym_xform *xform, struct rte_cryptodev_asym_session *sess) { - struct cnxk_ae_sess *priv = - (struct cnxk_ae_sess *) sess->sess_private_data; + struct cnxk_ae_sess *priv = (struct cnxk_ae_sess *)sess; struct cnxk_cpt_vf *vf = dev->data->dev_private; struct roc_cpt *roc_cpt = &vf->cpt; union cpt_inst_w7 w7; + struct hw_ctx_s *hwc; int ret; ret = cnxk_ae_fill_session_parameters(priv, xform); if (ret) return ret; + priv->lf = roc_cpt->lf[0]; + w7.u64 = 0; w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_AE]; + + if (vf->cpt.cpt_revision == ROC_CPT_REVISION_ID_106XX) { + hwc = &priv->hw_ctx; + hwc->w0.s.aop_valid = 1; + hwc->w0.s.ctx_hdr_size = 0; + hwc->w0.s.ctx_size = 1; + hwc->w0.s.ctx_push_size = 1; + + w7.s.cptr = (uint64_t)hwc; + w7.s.ctx_val = 1; + } + priv->cpt_inst_w7 = w7.u64; priv->cnxk_fpm_iova = vf->cnxk_fpm_iova; priv->ec_grp = vf->ec_grp;