From patchwork Thu Mar 9 14:36:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Marchand X-Patchwork-Id: 124906 X-Patchwork-Delegate: maxime.coquelin@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B08AC41E22; Thu, 9 Mar 2023 15:36:14 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A162D427F2; Thu, 9 Mar 2023 15:36:14 +0100 (CET) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id 89A8040ED7 for ; Thu, 9 Mar 2023 15:36:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1678372573; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=nWkngY1xItcpcwZgTRpNiqOIdO3PPEOzM+Vx6BbqwLk=; b=ImJTEd09RdWY6/7OLYWQUfhMDLGf5bWHBt5E96IRN6o4jQh/ShAv3Pzmeckheu9BufT43R NHrdQHYYulQX+yGdHT066vwmfUfWksbV716G0CNcM4l0ciRX1yJZ5YxtZ4eKKaILFjnjY4 z7iXX795r8QaF+P7T7vKVvMiInVkFYk= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-445-64gt-FwFPTGAO-XlGptGhg-1; Thu, 09 Mar 2023 09:36:10 -0500 X-MC-Unique: 64gt-FwFPTGAO-XlGptGhg-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2F6AF100F912; Thu, 9 Mar 2023 14:36:10 +0000 (UTC) Received: from dmarchan.redhat.com (unknown [10.45.224.63]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4763A140EBF4; Thu, 9 Mar 2023 14:36:09 +0000 (UTC) From: David Marchand To: dev@dpdk.org Cc: andy.pei@intel.com, Maxime Coquelin , Chenbo Xia Subject: [PATCH] net/virtio: remove address width limit for modern devices Date: Thu, 9 Mar 2023 15:36:04 +0100 Message-Id: <20230309143604.2354288-1-david.marchand@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Modern devices don't have the same limitation as legacy devices, because vring addresses are not configured using a 32-bit register. Signed-off-by: David Marchand Reviewed-by: Maxime Coquelin Acked-by: Andy Pei Reviewed-by: Chenbo Xia --- drivers/net/virtio/virtio_pci.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c index 9cf4d760b4..29eb739b04 100644 --- a/drivers/net/virtio/virtio_pci.c +++ b/drivers/net/virtio/virtio_pci.c @@ -33,22 +33,6 @@ struct virtio_pci_internal virtio_pci_internal[RTE_MAX_ETHPORTS]; -static inline int -check_vq_phys_addr_ok(struct virtqueue *vq) -{ - /* Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit, - * and only accepts 32 bit page frame number. - * Check if the allocated physical memory exceeds 16TB. - */ - if ((vq->vq_ring_mem + vq->vq_ring_size - 1) >> - (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) { - PMD_INIT_LOG(ERR, "vring address shouldn't be above 16TB!"); - return 0; - } - - return 1; -} - #define PCI_MSIX_ENABLE 0x8000 static enum virtio_msix_status @@ -273,8 +257,15 @@ legacy_setup_queue(struct virtio_hw *hw, struct virtqueue *vq) { uint32_t src; - if (!check_vq_phys_addr_ok(vq)) + /* Virtio PCI device VIRTIO_PCI_QUEUE_PFN register is 32bit, + * and only accepts 32 bit page frame number. + * Check if the allocated physical memory exceeds 16TB. + */ + if ((vq->vq_ring_mem + vq->vq_ring_size - 1) >> + (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) { + PMD_INIT_LOG(ERR, "vring address shouldn't be above 16TB!"); return -1; + } rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2, VIRTIO_PCI_QUEUE_SEL); @@ -476,9 +467,6 @@ modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq) uint64_t desc_addr, avail_addr, used_addr; uint16_t notify_off; - if (!check_vq_phys_addr_ok(vq)) - return -1; - desc_addr = vq->vq_ring_mem; avail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc); used_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,