From patchwork Fri Apr 28 14:46:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 126629 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 95D1E42A12; Fri, 28 Apr 2023 16:47:10 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BD6D242F88; Fri, 28 Apr 2023 16:47:04 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0917B40A87 for ; Fri, 28 Apr 2023 16:47:02 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33SA59pF003400 for ; Fri, 28 Apr 2023 07:47:02 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kwKP2wuaIopOxlf/lsPS6YtliyKBM/EsXiQ2W75yMYs=; b=gEy7Sr92x0KX8WmbqRiz6rKr0MQE3v3nJyeHJ3S8BNxCRb4UAcV0njC5d3kydT/HUw4U Z/WDYnst4cmNjQK1NO/BxfS08EQaxfLFgvo4N4G1ErLm49qOU4VmRByK83Lk3N0al0Uo VWLA896iWFpM7sxcF+9Jn0kaYLb+QH4r/peWuCNpxcfynLDXDvQamAy9VjeL0bDhgQLC z06vxjkgn6HKc9bdFv6J1Vofr9jvCqCRBJfX59UYFIVmB9NkSqF2Y1uY7m9ViTARa+C/ 7FGxp1NaxhcCHClXGmMgiXDNPG0I7A+1IdrlT1YKmskhIIUo+aRKB5E+PnY/1fBed3QF 1w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3q85x62axr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 28 Apr 2023 07:47:02 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 28 Apr 2023 07:47:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 28 Apr 2023 07:47:00 -0700 Received: from HY-LT1085.marvell.com (unknown [10.193.84.114]) by maili.marvell.com (Postfix) with ESMTP id 7D4B55B692C; Fri, 28 Apr 2023 07:46:57 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Aakash Sasidharan , Anoob Joseph , Jerin Jacob , "Gowrishankar Muthukrishnan" , Vidya Sagar Velumuri , Subject: [PATCH 2/7] crypto/cnxk: add cryptodev reconfiguration support Date: Fri, 28 Apr 2023 20:16:42 +0530 Message-ID: <20230428144647.1072-3-ktejasree@marvell.com> X-Mailer: git-send-email 2.40.1.windows.1 In-Reply-To: <20230428144647.1072-1-ktejasree@marvell.com> References: <20230428144647.1072-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 0cnXYjm-90PfP9cJd8m9r0_K3roabf9c X-Proofpoint-ORIG-GUID: 0cnXYjm-90PfP9cJd8m9r0_K3roabf9c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-28_04,2023-04-27_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Aakash Sasidharan Add support for reconfiguration of cryptodev on cnxk platforms. Signed-off-by: Aakash Sasidharan --- drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 46 +++++++++++++++--------- 1 file changed, 30 insertions(+), 16 deletions(-) diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 0f59a6c99c..85123d8afe 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -67,15 +67,42 @@ cnxk_cpt_asym_get_mlen(void) return len; } +static int +cnxk_cpt_dev_clear(struct rte_cryptodev *dev) +{ + struct cnxk_cpt_vf *vf = dev->data->dev_private; + int ret; + + if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) { + roc_ae_fpm_put(); + roc_ae_ec_grp_put(); + } + + ret = roc_cpt_int_misc_cb_unregister(cnxk_cpt_int_misc_cb, NULL); + if (ret < 0) { + plt_err("Could not unregister CPT_MISC_INT cb"); + return ret; + } + + roc_cpt_dev_clear(&vf->cpt); + + return 0; +} + int -cnxk_cpt_dev_config(struct rte_cryptodev *dev, - struct rte_cryptodev_config *conf) +cnxk_cpt_dev_config(struct rte_cryptodev *dev, struct rte_cryptodev_config *conf) { struct cnxk_cpt_vf *vf = dev->data->dev_private; struct roc_cpt *roc_cpt = &vf->cpt; uint16_t nb_lf_avail, nb_lf; int ret; + /* If this is a reconfigure attempt, clear the device and configure again */ + if (roc_cpt->nb_lf > 0) { + cnxk_cpt_dev_clear(dev); + roc_cpt->opaque = NULL; + } + dev->feature_flags = cnxk_cpt_default_ff_get() & ~conf->ff_disable; nb_lf_avail = roc_cpt->nb_lf_avail; @@ -151,7 +178,6 @@ cnxk_cpt_dev_stop(struct rte_cryptodev *dev) int cnxk_cpt_dev_close(struct rte_cryptodev *dev) { - struct cnxk_cpt_vf *vf = dev->data->dev_private; uint16_t i; int ret; @@ -163,19 +189,7 @@ cnxk_cpt_dev_close(struct rte_cryptodev *dev) } } - if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) { - roc_ae_fpm_put(); - roc_ae_ec_grp_put(); - } - - ret = roc_cpt_int_misc_cb_unregister(cnxk_cpt_int_misc_cb, NULL); - if (ret < 0) { - plt_err("Could not unregister CPT_MISC_INT cb"); - return ret; - } - roc_cpt_dev_clear(&vf->cpt); - - return 0; + return cnxk_cpt_dev_clear(dev); } void