From patchwork Fri Apr 28 14:46:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tejasree Kondoj X-Patchwork-Id: 126631 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 469C042A12; Fri, 28 Apr 2023 16:47:26 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 88E0342FB2; Fri, 28 Apr 2023 16:47:11 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 6522E40A87 for ; Fri, 28 Apr 2023 16:47:10 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33SA5AkB003420 for ; Fri, 28 Apr 2023 07:47:09 -0700 DKIM-Signature: v=1; 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Fri, 28 Apr 2023 07:47:07 -0700 Received: from HY-LT1085.marvell.com (unknown [10.193.84.114]) by maili.marvell.com (Postfix) with ESMTP id D40E95B6933; Fri, 28 Apr 2023 07:47:04 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Vidya Sagar Velumuri , Anoob Joseph , Jerin Jacob , Aakash Sasidharan , Gowrishankar Muthukrishnan , Subject: [PATCH 4/7] crypto/cnxk: support SM3 hash Date: Fri, 28 Apr 2023 20:16:44 +0530 Message-ID: <20230428144647.1072-5-ktejasree@marvell.com> X-Mailer: git-send-email 2.40.1.windows.1 In-Reply-To: <20230428144647.1072-1-ktejasree@marvell.com> References: <20230428144647.1072-1-ktejasree@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: uSn7-dn7qJ0hKoWSXEGKu5rbG3S1jPQi X-Proofpoint-ORIG-GUID: uSn7-dn7qJ0hKoWSXEGKu5rbG3S1jPQi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-28_04,2023-04-27_01,2023-02-09_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Add support for SM3 hash operations Signed-off-by: Vidya Sagar Velumuri --- doc/guides/cryptodevs/cnxk.rst | 1 + doc/guides/cryptodevs/features/cn10k.ini | 1 + drivers/common/cnxk/roc_se.h | 1 + drivers/crypto/cnxk/cnxk_cryptodev.h | 2 +- .../crypto/cnxk/cnxk_cryptodev_capabilities.c | 32 +++++++++++++++++++ drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 2 +- drivers/crypto/cnxk/cnxk_se.h | 12 ++++++- 7 files changed, 48 insertions(+), 3 deletions(-) diff --git a/doc/guides/cryptodevs/cnxk.rst b/doc/guides/cryptodevs/cnxk.rst index 3c2e38fefd..991bbc2f99 100644 --- a/doc/guides/cryptodevs/cnxk.rst +++ b/doc/guides/cryptodevs/cnxk.rst @@ -72,6 +72,7 @@ Hash algorithms: * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2`` * ``RTE_CRYPTO_AUTH_ZUC_EIA3`` * ``RTE_CRYPTO_AUTH_AES_CMAC`` +* ``RTE_CRYPTO_AUTH_SM3`` AEAD algorithms: diff --git a/doc/guides/cryptodevs/features/cn10k.ini b/doc/guides/cryptodevs/features/cn10k.ini index 162d1a25ca..f18b7f3d76 100644 --- a/doc/guides/cryptodevs/features/cn10k.ini +++ b/doc/guides/cryptodevs/features/cn10k.ini @@ -73,6 +73,7 @@ SHA3_512 = Y SHA3_512 HMAC = Y SHAKE_128 = Y SHAKE_256 = Y +SM3 = Y ; ; Supported AEAD algorithms of 'cn10k' crypto driver. diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h index 7771f22c66..1495088915 100644 --- a/drivers/common/cnxk/roc_se.h +++ b/drivers/common/cnxk/roc_se.h @@ -81,6 +81,7 @@ typedef enum { ROC_SE_SHA2_SHA512 = 6, ROC_SE_GMAC_TYPE = 7, ROC_SE_POLY1305 = 8, + ROC_SE_SM3 = 9, ROC_SE_SHA3_SHA224 = 10, ROC_SE_SHA3_SHA256 = 11, ROC_SE_SHA3_SHA384 = 12, diff --git a/drivers/crypto/cnxk/cnxk_cryptodev.h b/drivers/crypto/cnxk/cnxk_cryptodev.h index 32dec70264..ce45f5d01b 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev.h @@ -10,7 +10,7 @@ #include "roc_cpt.h" -#define CNXK_CPT_MAX_CAPS 48 +#define CNXK_CPT_MAX_CAPS 49 #define CNXK_SEC_CRYPTO_MAX_CAPS 16 #define CNXK_SEC_MAX_CAPS 9 #define CNXK_AE_EC_ID_MAX 8 diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c index 19956ffa07..0b02cea308 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_capabilities.c @@ -337,6 +337,29 @@ static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = { }, }; +static const struct rte_cryptodev_capabilities caps_sm3[] = { + { /* SM3 */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, + {.auth = { + .algo = RTE_CRYPTO_AUTH_SM3, + .block_size = 64, + .key_size = { + .min = 0, + .max = 0, + .increment = 0 + }, + .digest_size = { + .min = 32, + .max = 32, + .increment = 0 + }, + }, } + }, } + } +}; + static const struct rte_cryptodev_capabilities caps_sha3[] = { { /* SHA3_224 */ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, @@ -1459,6 +1482,12 @@ cn9k_crypto_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos cpt_caps_add(cnxk_caps, cur_pos, caps_docsis, RTE_DIM(caps_docsis)); } +static void +cn10k_crypto_caps_add(struct rte_cryptodev_capabilities cnxk_caps[], int *cur_pos) +{ + cpt_caps_add(cnxk_caps, cur_pos, caps_sm3, RTE_DIM(caps_sm3)); +} + static void crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[], union cpt_eng_caps *hw_caps) @@ -1477,6 +1506,9 @@ crypto_caps_populate(struct rte_cryptodev_capabilities cnxk_caps[], if (!roc_model_is_cn10k()) cn9k_crypto_caps_add(cnxk_caps, &cur_pos); + if (roc_model_is_cn10k()) + cn10k_crypto_caps_add(cnxk_caps, &cur_pos); + cpt_caps_add(cnxk_caps, &cur_pos, caps_null, RTE_DIM(caps_null)); cpt_caps_add(cnxk_caps, &cur_pos, caps_end, RTE_DIM(caps_end)); diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index dd35ee1278..649b5754c8 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -662,7 +662,7 @@ cnxk_cpt_inst_w7_get(struct cnxk_se_sess *sess, struct roc_cpt *roc_cpt) inst_w7.s.cptr += 8; /* Set the engine group */ - if (sess->zsk_flag || sess->aes_ctr_eea2 || sess->is_sha3) + if (sess->zsk_flag || sess->aes_ctr_eea2 || sess->is_sha3 || sess->is_sm3) inst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_SE]; else inst_w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE]; diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index 5fd89442d6..2c465a5ab9 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -44,7 +44,8 @@ struct cnxk_se_sess { uint16_t aad_length; uint8_t is_sha3 : 1; uint8_t short_iv : 1; - uint8_t rsvd : 6; + uint8_t is_sm3 : 1; + uint8_t rsvd : 5; uint8_t mac_len; uint8_t iv_length; uint8_t auth_iv_length; @@ -199,6 +200,9 @@ cpt_mac_len_verify(struct rte_crypto_auth_xform *auth) case RTE_CRYPTO_AUTH_SHAKE_256: ret = (mac_len <= UINT8_MAX) ? 0 : -1; break; + case RTE_CRYPTO_AUTH_SM3: + ret = (mac_len <= 32) ? 0 : -1; + break; case RTE_CRYPTO_AUTH_NULL: ret = 0; break; @@ -1999,6 +2003,7 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess) uint8_t zsk_flag = 0, zs_auth = 0, aes_gcm = 0, is_null = 0, is_sha3 = 0; struct rte_crypto_auth_xform *a_form; roc_se_auth_type auth_type = 0; /* NULL Auth type */ + uint8_t is_sm3 = 0; if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) return fill_sess_gmac(xform, sess); @@ -2109,6 +2114,10 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess) auth_type = ROC_SE_AES_CMAC_EIA2; zsk_flag = ROC_SE_ZS_IA; break; + case RTE_CRYPTO_AUTH_SM3: + auth_type = ROC_SE_SM3; + is_sm3 = 1; + break; case RTE_CRYPTO_AUTH_AES_XCBC_MAC: case RTE_CRYPTO_AUTH_AES_CBC_MAC: plt_dp_err("Crypto: Unsupported hash algo %u", a_form->algo); @@ -2136,6 +2145,7 @@ fill_sess_auth(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess) sess->mac_len = a_form->digest_length; sess->is_null = is_null; sess->is_sha3 = is_sha3; + sess->is_sm3 = is_sm3; if (zsk_flag) { sess->auth_iv_offset = a_form->iv.offset; sess->auth_iv_length = a_form->iv.length;