From patchwork Tue May 23 20:03:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 127250 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 81A5042B85; Tue, 23 May 2023 22:04:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6FE0E42D35; Tue, 23 May 2023 22:04:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3994742D33 for ; Tue, 23 May 2023 22:04:30 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34NBqZHi029337; Tue, 23 May 2023 13:04:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=6D0/fAy/rYsJZmC2jLM0sQ04QVMpaSpNBQzIQQqF/Cc=; b=NSJV0XfrBwkwSJohogkdh6mUmC/cyUkzMSulkIzvx9BqA1Y0L7uB4NzVtIxn208fRnFZ nuzPRodPXdoxNLqz+W984v8aLTZ3AxQapO1WGSLbt+/tkWYRMLEN5y7Ysw6gttVNs4NF rCmsA4oHgZMdnWNy2OoloSbGgzFla7Fb1HJSt19vwIXO0NKY4K00Q2hWY1SZiKkSO0Jy ZjDgyuW7naIz5EezryITNztoYYouS8D+YFKAZm2psIauPrMYufKs+02VcSA6hqvBzFtd JegJvVxXYVmqA+0hjPdyGAGdzHuOO3Yg5L1OMsJ0kAv//9DBBxSMDVBu/vwSiYIkdrg5 tg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qrm46mdy5-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 23 May 2023 13:04:26 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 23 May 2023 13:04:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 23 May 2023 13:04:20 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id 9CBA83F70B5; Tue, 23 May 2023 13:04:17 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , , , , Akhil Goyal Subject: [PATCH 03/15] common/cnxk: add MACsec SC configuration APIs Date: Wed, 24 May 2023 01:33:49 +0530 Message-ID: <20230523200401.1945974-4-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230523200401.1945974-1-gakhil@marvell.com> References: <20220928124516.93050-1-gakhil@marvell.com> <20230523200401.1945974-1-gakhil@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: mZTW6BxiRqL9AaivDhEc4Apqod81Hu1Q X-Proofpoint-GUID: mZTW6BxiRqL9AaivDhEc4Apqod81Hu1Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-23_12,2023-05-23_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs to configure MACsec secure channel(SC) and its mapping with SAs for both Rx and Tx. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/roc_mbox.h | 37 ++++++ drivers/common/cnxk/roc_mcs.h | 41 ++++++ drivers/common/cnxk/roc_mcs_sec_cfg.c | 171 ++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 7 ++ 4 files changed, 256 insertions(+) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 66a6de2cd2..0673c31389 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -280,7 +280,10 @@ struct mbox_msghdr { M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ mcs_alloc_rsrc_rsp) \ M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ + M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, msg_rsp) \ M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, msg_rsp) \ + M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, msg_rsp) \ + M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, msg_rsp) \ M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ @@ -706,6 +709,16 @@ struct mcs_free_rsrc_req { uint64_t __io rsvd; }; +/* RX SC_CAM mapping */ +struct mcs_rx_sc_cam_write_req { + struct mbox_msghdr hdr; + uint64_t __io sci; /* SCI */ + uint64_t __io secy_id; /* secy index mapped to SC */ + uint8_t __io sc_id; /* SC CAM entry index */ + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; + struct mcs_sa_plcy_write_req { struct mbox_msghdr hdr; uint64_t __io plcy[2][9]; /* Support 2 SA policy */ @@ -716,6 +729,30 @@ struct mcs_sa_plcy_write_req { uint64_t __io rsvd; }; +struct mcs_tx_sc_sa_map { + struct mbox_msghdr hdr; + uint8_t __io sa_index0; + uint8_t __io sa_index1; + uint8_t __io rekey_ena; + uint8_t __io sa_index0_vld; + uint8_t __io sa_index1_vld; + uint8_t __io tx_sa_active; + uint64_t __io sectag_sci; + uint8_t __io sc_id; /* used as index for SA_MEM_MAP */ + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; + +struct mcs_rx_sc_sa_map { + struct mbox_msghdr hdr; + uint8_t __io sa_index; + uint8_t __io sa_in_use; + uint8_t __io sc_id; + /* an range is 0-3, sc_id + an used as index SA_MEM_MAP */ + uint8_t __io an; + uint8_t __io mcs_id; + uint64_t __io rsvd; +}; struct mcs_hw_info { struct mbox_msghdr hdr; diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index a345d2a880..2787d6a940 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -32,6 +32,12 @@ struct roc_mcs_free_rsrc_req { uint8_t all; /* Free all the cam resources */ }; +/* RX SC_CAM mapping */ +struct roc_mcs_rx_sc_cam_write_req { + uint64_t sci; /* SCI */ + uint64_t secy_id; /* secy index mapped to SC */ + uint8_t sc_id; /* SC CAM entry index */ +}; struct roc_mcs_sa_plcy_write_req { uint64_t plcy[2][9]; @@ -40,6 +46,24 @@ struct roc_mcs_sa_plcy_write_req { uint8_t dir; }; +struct roc_mcs_tx_sc_sa_map { + uint8_t sa_index0; + uint8_t sa_index1; + uint8_t rekey_ena; + uint8_t sa_index0_vld; + uint8_t sa_index1_vld; + uint8_t tx_sa_active; + uint64_t sectag_sci; + uint8_t sc_id; /* used as index for SA_MEM_MAP */ +}; + +struct roc_mcs_rx_sc_sa_map { + uint8_t sa_index; + uint8_t sa_in_use; + uint8_t sc_id; + uint8_t an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */ +}; + struct roc_mcs_hw_info { uint8_t num_mcs_blks; /* Number of MCS blocks */ uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ @@ -79,4 +103,21 @@ __roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy); __roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy); +/* RX SC read, write and enable */ +__roc_api int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); +__roc_api int roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); +__roc_api int roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam); +/* RX SC-SA MAP read and write */ +__roc_api int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map); +__roc_api int roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs, + struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map); +/* TX SC-SA MAP read and write */ +__roc_api int roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, + struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map); +__roc_api int roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs, + struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map); #endif /* _ROC_MCS_H_ */ diff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c index 50f2352c20..04bbbbfda0 100644 --- a/drivers/common/cnxk/roc_mcs_sec_cfg.c +++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c @@ -209,3 +209,174 @@ roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused, return -ENOTSUP; } + + +int +roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_rx_sc_cam_write_req *rx_sc; + struct msg_rsp *rsp; + int rc; + + MCS_SUPPORT_CHECK; + + if (rx_sc_cam == NULL) + return -EINVAL; + + rx_sc = mbox_alloc_msg_mcs_rx_sc_cam_write(mcs->mbox); + if (rx_sc == NULL) + return -ENOMEM; + + rx_sc->sci = rx_sc_cam->sci; + rx_sc->secy_id = rx_sc_cam->secy_id; + rx_sc->sc_id = rx_sc_cam->sc_id; + rx_sc->mcs_id = mcs->idx; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + for (int i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].secy_bmap, rx_sc_cam->secy_id); + + if (set) { + plt_bitmap_set(priv->port_rsrc[i].sc_bmap, rx_sc_cam->sc_id); + break; + } + } + + return 0; +} + +int +roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + +int +roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + +int +roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_rx_sc_sa_map *sa_map; + struct msg_rsp *rsp; + uint16_t sc_id; + int rc; + + MCS_SUPPORT_CHECK; + + if (rx_sc_sa_map == NULL) + return -EINVAL; + + sc_id = rx_sc_sa_map->sc_id; + sa_map = mbox_alloc_msg_mcs_rx_sc_sa_map_write(mcs->mbox); + if (sa_map == NULL) + return -ENOMEM; + + sa_map->sa_index = rx_sc_sa_map->sa_index; + sa_map->sa_in_use = rx_sc_sa_map->sa_in_use; + sa_map->sc_id = rx_sc_sa_map->sc_id; + sa_map->an = rx_sc_sa_map->an; + sa_map->mcs_id = mcs->idx; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + for (int i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].sc_bmap, sc_id); + + if (set) { + plt_bitmap_set(priv->port_rsrc[i].sa_bmap, rx_sc_sa_map->sa_index); + priv->port_rsrc[i].sc_conf[sc_id].rx.sa_idx = rx_sc_sa_map->sa_index; + priv->port_rsrc[i].sc_conf[sc_id].rx.an = rx_sc_sa_map->an; + break; + } + } + + return 0; +} + +int +roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} + +int +roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_tx_sc_sa_map *sa_map; + struct msg_rsp *rsp; + uint16_t sc_id; + int rc; + + MCS_SUPPORT_CHECK; + + if (tx_sc_sa_map == NULL) + return -EINVAL; + + sa_map = mbox_alloc_msg_mcs_tx_sc_sa_map_write(mcs->mbox); + if (sa_map == NULL) + return -ENOMEM; + + sa_map->sa_index0 = tx_sc_sa_map->sa_index0; + sa_map->sa_index1 = tx_sc_sa_map->sa_index1; + sa_map->rekey_ena = tx_sc_sa_map->rekey_ena; + sa_map->sa_index0_vld = tx_sc_sa_map->sa_index0_vld; + sa_map->sa_index1_vld = tx_sc_sa_map->sa_index1_vld; + sa_map->tx_sa_active = tx_sc_sa_map->tx_sa_active; + sa_map->sectag_sci = tx_sc_sa_map->sectag_sci; + sa_map->sc_id = tx_sc_sa_map->sc_id; + sa_map->mcs_id = mcs->idx; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + sc_id = tx_sc_sa_map->sc_id; + for (int i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].sc_bmap, sc_id + priv->sc_entries); + + if (set) { + uint32_t pos = priv->sa_entries + tx_sc_sa_map->sa_index0; + + plt_bitmap_set(priv->port_rsrc[i].sa_bmap, pos); + priv->port_rsrc[i].sc_conf[sc_id].tx.sa_idx0 = tx_sc_sa_map->sa_index0; + pos = priv->sa_entries + tx_sc_sa_map->sa_index1; + plt_bitmap_set(priv->port_rsrc[i].sa_bmap, pos); + priv->port_rsrc[i].sc_conf[sc_id].tx.sa_idx1 = tx_sc_sa_map->sa_index1; + priv->port_rsrc[i].sc_conf[sc_id].tx.sci = tx_sc_sa_map->sectag_sci; + priv->port_rsrc[i].sc_conf[sc_id].tx.rekey_enb = tx_sc_sa_map->rekey_ena; + break; + } + } + + return 0; +} + +int +roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 9266edd9a1..a1af736a07 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -139,8 +139,15 @@ INTERNAL { roc_mcs_dev_get; roc_mcs_free_rsrc; roc_mcs_hw_info_get; + roc_mcs_rx_sc_cam_enable; + roc_mcs_rx_sc_cam_read; + roc_mcs_rx_sc_cam_write; + roc_mcs_rx_sc_sa_map_read; + roc_mcs_rx_sc_sa_map_write; roc_mcs_sa_policy_read; roc_mcs_sa_policy_write; + roc_mcs_tx_sc_sa_map_read; + roc_mcs_tx_sc_sa_map_write; roc_nix_bpf_alloc; roc_nix_bpf_config; roc_nix_bpf_connect;