From patchwork Thu May 25 09:58:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 127433 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AF4B642B9A; Thu, 25 May 2023 12:38:31 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3DDBC42D43; Thu, 25 May 2023 12:38:29 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 0F4C840DF8 for ; Thu, 25 May 2023 12:38:25 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34PA2X1M020293 for ; Thu, 25 May 2023 03:38:25 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=EeWaPYelPMNytQ+EPBCmgFaAxZaFpnKVxc80DtcWxkA=; b=CWnCJAUB5ff7lDoY2zA9PtOsLCtGAnJRIjAkd+Zh6G9JVU8jqOu7FK9G6/6eUQNV84Yf ejORs27+WMYxYtnQsmZbadxGdpQJgkisqToqLIdj9dIbzF7NLvK+tQOxCQFyUz1PLoGX JHyarH6K+12NA/4IA5ZqK6vbbReN91UplEGncC0bkc63hGobQOz8jTqnEskBNbp6ga7c 9+3OwiZerZijFamW1DyOmbRlHkuaeIAM3lOUQ2Z5ctyimiAJtvZfKvYC5H3Dz1MWOseE w1zm1gu08pm1DqrNu2UebQF6iwZo67VW+rvm2+ukPRDyFfrtOV2nPKuuJHh5g9COKmBn +A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3qt5jng44q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 25 May 2023 03:38:25 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 25 May 2023 03:38:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 25 May 2023 03:38:23 -0700 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 15F9B5B6BC6; Thu, 25 May 2023 02:59:49 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Kumar Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Rakesh Kudurumalla Subject: [PATCH v3 11/32] common/cnxk: add receive error mask Date: Thu, 25 May 2023 15:28:43 +0530 Message-ID: <20230525095904.3967080-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230525095904.3967080-1-ndabilpuram@marvell.com> References: <20230411091144.1087887-1-ndabilpuram@marvell.com> <20230525095904.3967080-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: mXx1BTKCycDZpHCEO0UexpAGGj-mDU1a X-Proofpoint-GUID: mXx1BTKCycDZpHCEO0UexpAGGj-mDU1a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-25_06,2023-05-24_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rakesh Kudurumalla Adding support to configure receive error mask for 106B0 Signed-off-by: Rakesh Kudurumalla --- drivers/common/cnxk/roc_features.h | 6 ++++++ drivers/common/cnxk/roc_nix.h | 16 ++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/common/cnxk/roc_features.h b/drivers/common/cnxk/roc_features.h index 6fe01015d8..ce12a1dca4 100644 --- a/drivers/common/cnxk/roc_features.h +++ b/drivers/common/cnxk/roc_features.h @@ -16,6 +16,12 @@ roc_feature_nix_has_inl_ipsec_mseg(void) return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0()); } +static inline bool +roc_feature_nix_has_drop_re_mask(void) +{ + return (roc_model_is_cn10kb() || roc_model_is_cn10ka_b0()); +} + static inline bool roc_feature_nix_has_inl_rq_mask(void) { diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index f84e473db6..37d0ed5ebe 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -242,6 +242,22 @@ struct roc_nix_eeprom_info { #define ROC_NIX_LF_RX_CFG_LEN_OL4 BIT_ULL(40) #define ROC_NIX_LF_RX_CFG_LEN_OL3 BIT_ULL(41) +#define ROC_NIX_LF_RX_CFG_RX_ERROR_MASK 0xFFFFFFFFFFF80000 +#define ROC_NIX_RE_PARTIAL BIT_ULL(1) +#define ROC_NIX_RE_JABBER BIT_ULL(2) +#define ROC_NIX_RE_CRC8_PCH BIT_ULL(5) +#define ROC_NIX_RE_CNC_INV BIT_ULL(6) +#define ROC_NIX_RE_FCS BIT_ULL(7) +#define ROC_NIX_RE_FCS_RCV BIT_ULL(8) +#define ROC_NIX_RE_TERMINATE BIT_ULL(9) +#define ROC_NIX_RE_MACSEC BIT_ULL(10) +#define ROC_NIX_RE_RX_CTL BIT_ULL(11) +#define ROC_NIX_RE_SKIP BIT_ULL(12) +#define ROC_NIX_RE_DMAPKT BIT_ULL(15) +#define ROC_NIX_RE_UNDERSIZE BIT_ULL(16) +#define ROC_NIX_RE_OVERSIZE BIT_ULL(17) +#define ROC_NIX_RE_OL2_LENMISM BIT_ULL(18) + /* Group 0 will be used for RSS, 1 -7 will be used for npc_flow RSS action*/ #define ROC_NIX_RSS_GROUP_DEFAULT 0 #define ROC_NIX_RSS_GRPS 8