From patchwork Tue May 30 09:39:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srujana Challa X-Patchwork-Id: 127700 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 61B7D42BE1; Tue, 30 May 2023 11:40:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E0E0340A82; Tue, 30 May 2023 11:40:05 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 57B7D406BC for ; Tue, 30 May 2023 11:40:04 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34U8wV6q010724 for ; Tue, 30 May 2023 02:40:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=UwCVuJCGzuXnmn7Yvl4itbpRiBdi4RWl3WgdInHn/Sg=; b=kPfyWaOBBeltloXIS0F8Q8F0lwr1lW5RwUE1LFXx+LJKxr2flfxN8qChEr6FKOMVl4MZ l2IRVcpZMfsoHyzsrNaJ+scDs2Lf3aOEYYzZsReK7/KeA43/58HdobSsbATPxxH8ujeT Kfn512DwEVVLCEp7Le0psZflvk2vqdXHOgR6xo0ZeNl9vnNAlehNiXfwRbLdnjRsYuGW a7XD+WnLlUKecaTSA4satjSPUyzghZZicu5a/MtKkdk7rqqLeDyA9WfqT4h7V5gB9k4h oDZb+fI0o4rs2hRp50VN2S+q0isdmrZFQVJ4TLQndQbEX7MrxKDzuRWsNmtCqQf6uiop /w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3quhcm7rqh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 30 May 2023 02:40:03 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 30 May 2023 02:40:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 30 May 2023 02:40:01 -0700 Received: from localhost.localdomain (unknown [10.28.36.175]) by maili.marvell.com (Postfix) with ESMTP id B3C083F7043; Tue, 30 May 2023 02:39:58 -0700 (PDT) From: Srujana Challa To: , , , CC: , , , sa_ip-toolkits-Jenkins Subject: [PATCH] event/cnxk: add wmb after steorl for event mode Date: Tue, 30 May 2023 15:09:57 +0530 Message-ID: <20230530093957.3438848-1-schalla@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Proofpoint-GUID: -ZMzH4FPfPZe2usAvV4Vg2XzPzI2nh7_ X-Proofpoint-ORIG-GUID: -ZMzH4FPfPZe2usAvV4Vg2XzPzI2nh7_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-30_06,2023-05-29_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Author Srujana Challa LMTST area can be overwritten before read by HW between to consecutive steorl operations. Hence, add wmb() after steorl op to make sure the lmtst operation is complete. Signed-off-by: Srujana Challa Change-Id: Ib16d7cd88cff79e9ca78eff8c47b7ddad2d234dd Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/dataplane/dpdk/+/103549 Base-Builds: sa_ip-toolkits-Jenkins Tested-by: sa_ip-toolkits-Jenkins Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/event/cnxk/cn10k_tx_worker.h | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/event/cnxk/cn10k_tx_worker.h b/drivers/event/cnxk/cn10k_tx_worker.h index c18786a14c..81fe31c4b9 100644 --- a/drivers/event/cnxk/cn10k_tx_worker.h +++ b/drivers/event/cnxk/cn10k_tx_worker.h @@ -43,7 +43,6 @@ cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd, const uint64_t *txq_data, const uint32_t flags) { uint8_t lnum = 0, loff = 0, shft = 0; - uint16_t ref_cnt = m->refcnt; struct cn10k_eth_txq *txq; uintptr_t laddr; uint16_t segdw; @@ -98,10 +97,9 @@ cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd, roc_lmt_submit_steorl(lmt_id, pa); - if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) { - if (ref_cnt > 1) - rte_io_wmb(); - } + /* Memory barrier to make sure lmtst store completes */ + rte_io_wmb(); + return 1; }