From patchwork Mon Sep 4 09:26:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Morten_Br=C3=B8rup?= X-Patchwork-Id: 131147 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 035CC424EE; Mon, 4 Sep 2023 11:26:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E5501402AF; Mon, 4 Sep 2023 11:26:35 +0200 (CEST) Received: from dkmailrelay1.smartsharesystems.com (smartserver.smartsharesystems.com [77.243.40.215]) by mails.dpdk.org (Postfix) with ESMTP id 3B738400EF for ; Mon, 4 Sep 2023 11:26:35 +0200 (CEST) Received: from smartserver.smartsharesystems.com (smartserver.smartsharesys.local [192.168.4.10]) by dkmailrelay1.smartsharesystems.com (Postfix) with ESMTP id 112D42089E; Mon, 4 Sep 2023 11:26:35 +0200 (CEST) Received: from dkrd2.smartsharesys.local ([192.168.4.12]) by smartserver.smartsharesystems.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 4 Sep 2023 11:26:33 +0200 From: =?utf-8?q?Morten_Br=C3=B8rup?= To: thomas@monjalon.net, david.marchand@redhat.com, mattias.ronnblom@ericsson.com, bruce.richardson@intel.com Cc: olivier.matz@6wind.com, andrew.rybchenko@oktetlabs.ru, honnappa.nagarahalli@arm.com, konstantin.v.ananyev@yandex.ru, dev@dpdk.org, =?utf-8?q?Morten_Br=C3=B8rup?= Subject: [PATCH] eal: add cache guard to per-lcore PRNG state Date: Mon, 4 Sep 2023 11:26:32 +0200 Message-Id: <20230904092632.12675-1-mb@smartsharesystems.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-OriginalArrivalTime: 04 Sep 2023 09:26:33.0540 (UTC) FILETIME=[E51C1040:01D9DF11] X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The per-lcore random state is frequently updated by their individual lcores, so add a cache guard to prevent CPU cache thrashing. Depends-on: series-29415 ("clarify purpose of empty cache lines") Signed-off-by: Morten Brørup Acked-by: Mattias Rönnblom Signed-off-by: Stephen Hemminger --- lib/eal/common/rte_random.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/eal/common/rte_random.c b/lib/eal/common/rte_random.c index 565f2401ce..3df0c7004a 100644 --- a/lib/eal/common/rte_random.c +++ b/lib/eal/common/rte_random.c @@ -18,6 +18,7 @@ struct rte_rand_state { uint64_t z3; uint64_t z4; uint64_t z5; + RTE_CACHE_GUARD; } __rte_cache_aligned; /* One instance each for every lcore id-equipped thread, and one