From patchwork Tue Oct 31 12:23:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Hai X-Patchwork-Id: 133662 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A190A43252; Tue, 31 Oct 2023 13:35:46 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8C5F64067C; Tue, 31 Oct 2023 13:35:42 +0100 (CET) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by mails.dpdk.org (Postfix) with ESMTP id 998DD4026C for ; Tue, 31 Oct 2023 13:35:39 +0100 (CET) Received: from kwepemi500020.china.huawei.com (unknown [172.30.72.55]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4SKTyr0DkHzPnb0 for ; Tue, 31 Oct 2023 20:31:32 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemi500020.china.huawei.com (7.221.188.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 31 Oct 2023 20:35:37 +0800 From: Jie Hai To: , Yisen Zhuang , "Wei Hu (Xavier)" , Chengchang Tang , Chengwen Feng , Huisong Li CC: Subject: [PATCH 1/6] net/hns3: fix setting DCB capability Date: Tue, 31 Oct 2023 20:23:54 +0800 Message-ID: <20231031122359.3930935-2-haijie1@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20231031122359.3930935-1-haijie1@huawei.com> References: <20231031122359.3930935-1-haijie1@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.2] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500020.china.huawei.com (7.221.188.8) X-CFilter-Loop: Reflected X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Huisong Li The "hw->capability" is set after querying firmware and version. But the DCB capability of PF is set in other place. So this patch moves setting DCB capability to the place where all capabilities are set. Fixes: ab2e2e344163 ("net/hns3: get device capability in primary process") Cc: stable@dpdk.org Signed-off-by: Huisong Li Signed-off-by: Jie Hai --- drivers/net/hns3/hns3_cmd.c | 25 +++++++++++++++++++++++++ drivers/net/hns3/hns3_ethdev.c | 13 ------------- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c index ca1d3f1b8c0d..62c55f347fa3 100644 --- a/drivers/net/hns3/hns3_cmd.c +++ b/drivers/net/hns3/hns3_cmd.c @@ -525,6 +525,28 @@ hns3_build_api_caps(void) return rte_cpu_to_le_32(api_caps); } +static void +hns3_set_dcb_capability(struct hns3_hw *hw) +{ + struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); + struct rte_pci_device *pci_dev; + struct rte_eth_dev *eth_dev; + uint16_t device_id; + + if (hns->is_vf) + return; + + eth_dev = &rte_eth_devices[hw->data->port_id]; + pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + device_id = pci_dev->id.device_id; + + if (device_id == HNS3_DEV_ID_25GE_RDMA || + device_id == HNS3_DEV_ID_50GE_RDMA || + device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || + device_id == HNS3_DEV_ID_200G_RDMA) + hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); +} + static int hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw) { @@ -542,6 +564,9 @@ hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw) return ret; hw->fw_version = rte_le_to_cpu_32(resp->firmware); + + hns3_set_dcb_capability(hw); + /* * Make sure mask the capability before parse capability because it * may overwrite resp's data. diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 964f47f1641e..29f9625b4036 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2669,22 +2669,9 @@ static int hns3_get_capability(struct hns3_hw *hw) { struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); - struct rte_pci_device *pci_dev; struct hns3_pf *pf = &hns->pf; - struct rte_eth_dev *eth_dev; - uint16_t device_id; int ret; - eth_dev = &rte_eth_devices[hw->data->port_id]; - pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); - device_id = pci_dev->id.device_id; - - if (device_id == HNS3_DEV_ID_25GE_RDMA || - device_id == HNS3_DEV_ID_50GE_RDMA || - device_id == HNS3_DEV_ID_100G_RDMA_MACSEC || - device_id == HNS3_DEV_ID_200G_RDMA) - hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_DCB_B, 1); - ret = hns3_get_pci_revision_id(hw, &hw->revision); if (ret) return ret;