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Sun, 3 Dec 2023 03:26:29 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Alex Vesker Subject: [PATCH v1 17/23] net/mlx5/hws: support GENEVE matching Date: Sun, 3 Dec 2023 13:25:37 +0200 Message-ID: <20231203112543.844014-18-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231203112543.844014-1-michaelba@nvidia.com> References: <20231203112543.844014-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709B:EE_|SN7PR12MB8772:EE_ X-MS-Office365-Filtering-Correlation-Id: 12b699e5-4ea5-4d41-6f3b-08dbf3f2b934 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uNmzjb8gwUxQ47Ws1DgJMph0ev7Mp96LFeq7E8l5F/j+iDNb2rWXTzTquDjcDDURjni9sOMUYEeYzWCgPaWOV1LfdLKGpLEj7T+oNtFjsquIZRk/Sq8oSU9Rl5hcAa9crIdsWUciFU1nh27O3yj9rr5R5aWWbcjLDMVDREDObSMuGO/MkHs6ZNqkRGkNwwCKdNjLm+xCLSlbD7REk50qGBTk+R9y+qnMcwNWJ6/cBpJCHP8EjRBqqvfh8tIW5qx+6IgldAmPw8QCqnyVAcuOK/3Qdysg/ycJDy7Hul0I4gQMOEXU5nwUTGH0dLtZxtI5nE3LA2b3uZYWKpmPXzWOpLYushsshz8LTn1fyCQlTDYyJYqCP1W1b8Pr7KdBuv8482fQ27hWNQMuOfo76Mrfh+YeDoS4RotbPVUVNPj0ksLl31n9B6vWK/X+jlW43uJeqSK4CTCpja4ormxqhxlGrV35ErFHPOAUwlEWKq+BB3IV/WOpqLdNtxLsX6rsTOgtYE0vgFy9OkS+TWFwTNJOJV9kDnh7xoBUoUphKImowFPjMXZoU9/Qk1wbO+QbN4XIRYFKYoWcHvMcYjZBnvWCPrbkXS16mRI0l/9tDdvfHaZwhOhZTWjCjpEM720RRhVBVvkQ6AwB7wxGhjtTyGy+WTm40rsI1N9KuQ27VS7y2QqxMCzimt0Y50OgEWA4v28NoCDATvwGmMeyJYjXe7dv48kMzKPnyBKnt4SqC2YjPIaX2mOTvW2m4BibRy8s7VIL X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8772 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker Add matching for GENEVE tunnel header. Signed-off-by: Alex Vesker --- drivers/net/mlx5/hws/mlx5dr_definer.c | 91 +++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_definer.h | 19 ++++++ 2 files changed, 110 insertions(+) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index bab1869369..141941c309 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -11,6 +11,7 @@ #define UDP_GTPU_PORT 2152 #define UDP_VXLAN_PORT 4789 #define UDP_PORT_MPLS 6635 +#define UDP_GENEVE_PORT 6081 #define UDP_ROCEV2_PORT 4791 #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS) @@ -172,6 +173,9 @@ struct mlx5dr_definer_conv_data { X(SET, source_qp, v->queue, mlx5_rte_flow_item_sq) \ X(SET, tag, v->data, rte_flow_item_tag) \ X(SET, metadata, v->data, rte_flow_item_meta) \ + X(SET_BE16, geneve_protocol, v->protocol, rte_flow_item_geneve) \ + X(SET, geneve_udp_port, UDP_GENEVE_PORT, rte_flow_item_geneve) \ + X(SET_BE16, geneve_ctrl, v->ver_opt_len_o_c_rsvd0, rte_flow_item_geneve) \ X(SET_BE16, gre_c_ver, v->c_rsvd0_ver, rte_flow_item_gre) \ X(SET_BE16, gre_protocol_type, v->protocol, rte_flow_item_gre) \ X(SET, ipv4_protocol_gre, IPPROTO_GRE, rte_flow_item_gre) \ @@ -682,6 +686,16 @@ mlx5dr_definer_mpls_label_set(struct mlx5dr_definer_fc *fc, memcpy(tag + fc->byte_off + sizeof(v->label_tc_s), &v->ttl, sizeof(v->ttl)); } +static void +mlx5dr_definer_geneve_vni_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_geneve *v = item_spec; + + memcpy(tag + fc->byte_off, v->vni, sizeof(v->vni)); +} + static void mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc, const void *item_spec, @@ -2172,6 +2186,79 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_geneve(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_geneve *m = item->mask; + struct mlx5dr_definer_fc *fc; + bool inner = cd->tunnel; + + if (inner) { + DR_LOG(ERR, "Inner GENEVE item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + + /* In order to match on Geneve we must match on ip_protocol and l4_dport */ + if (!cd->relaxed) { + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->tag_set = &mlx5dr_definer_udp_protocol_set; + DR_CALC_SET(fc, eth_l2, l4_type_bwc, inner); + } + + fc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->tag_set = &mlx5dr_definer_geneve_udp_port_set; + DR_CALC_SET(fc, eth_l4, destination_port, inner); + } + } + + if (!m) + return 0; + + if (m->rsvd1) { + rte_errno = ENOTSUP; + return rte_errno; + } + + if (m->ver_opt_len_o_c_rsvd0) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_GENEVE_CTRL]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_geneve_ctrl_set; + DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0); + fc->bit_mask = __mlx5_mask(header_geneve, ver_opt_len_o_c_rsvd); + fc->bit_off = __mlx5_dw_bit_off(header_geneve, ver_opt_len_o_c_rsvd); + } + + if (m->protocol) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_GENEVE_PROTO]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_geneve_protocol_set; + DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0); + fc->byte_off += MLX5_BYTE_OFF(header_geneve, protocol_type); + fc->bit_mask = __mlx5_mask(header_geneve, protocol_type); + fc->bit_off = __mlx5_dw_bit_off(header_geneve, protocol_type); + } + + if (!is_mem_zero(m->vni, 3)) { + fc = &cd->fc[MLX5DR_DEFINER_FNAME_GENEVE_VNI]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_geneve_vni_set; + DR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1); + fc->bit_mask = __mlx5_mask(header_geneve, vni); + fc->bit_off = __mlx5_dw_bit_off(header_geneve, vni); + } + + return 0; +} + static int mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt, struct mlx5dr_definer_fc *fc, @@ -2528,6 +2615,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, item_flags |= MLX5_FLOW_LAYER_MPLS; cd.mpls_idx++; break; + case RTE_FLOW_ITEM_TYPE_GENEVE: + ret = mlx5dr_definer_conv_item_geneve(&cd, items, i); + item_flags |= MLX5_FLOW_LAYER_GENEVE; + break; case RTE_FLOW_ITEM_TYPE_IB_BTH: ret = mlx5dr_definer_conv_item_ib_l4(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_IB_BTH; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index e2be579303..c09c0be62e 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -91,6 +91,9 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_VPORT_REG_C_0, MLX5DR_DEFINER_FNAME_VXLAN_FLAGS, MLX5DR_DEFINER_FNAME_VXLAN_VNI, + MLX5DR_DEFINER_FNAME_GENEVE_CTRL, + MLX5DR_DEFINER_FNAME_GENEVE_PROTO, + MLX5DR_DEFINER_FNAME_GENEVE_VNI, MLX5DR_DEFINER_FNAME_SOURCE_QP, MLX5DR_DEFINER_FNAME_REG_0, MLX5DR_DEFINER_FNAME_REG_1, @@ -608,6 +611,22 @@ struct mlx5_ifc_header_gre_bits { u8 reserved_at_30[0x10]; }; +struct mlx5_ifc_header_geneve_bits { + union { + u8 ver_opt_len_o_c_rsvd[0x10]; + struct { + u8 version[0x2]; + u8 opt_len[0x6]; + u8 o_flag[0x1]; + u8 c_flag[0x1]; + u8 reserved_at_a[0x6]; + }; + }; + u8 protocol_type[0x10]; + u8 vni[0x18]; + u8 reserved_at_38[0x8]; +}; + struct mlx5_ifc_header_icmp_bits { union { u8 icmp_dw1[0x20];