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Sun, 3 Dec 2023 03:26:07 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v1 08/23] common/mlx5: add PRM attribute for TLV sample Date: Sun, 3 Dec 2023 13:25:28 +0200 Message-ID: <20231203112543.844014-9-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231203112543.844014-1-michaelba@nvidia.com> References: <20231203112543.844014-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017097:EE_|CYYPR12MB8731:EE_ X-MS-Office365-Filtering-Correlation-Id: 9d582ca6-f92d-4e3d-b131-08dbf3f2aa87 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /Y/v4ufscisvYjWVbaJeMcH88bWIYcCtnHW+phKwQEjErbTA3h+KC/ldxfKzJ5vPKz46kakbLB/o0+JNzRc81wrwObN/tMSuR6BLCGq8/3T30T+a6UCslCQQ/ZI7fhwqjJYdHuAlBILF14KkAUXPJtmr5xvQpCiLVn7HGo4kzAGjQ27l4wCzLmKTBTyisjzFQWI1siJ1AK9UVF6zaOolKXkmQiCnKjh1W/acXUs1PzGZ685Fa8Iw6ncwilDShX/0du6OOXsJ8NHIz0aOyKZFQCBqoJpx6dtARAhmqSSTIr7QQd0LDR/u74+twor+2SHFyWDm7MrnHURJWBV7WLaIKFDLa7dpbd0q1ZSJP4wRHKVXzD1DU6jP/PDtRNnlxN9byDItp30MvGnqksFdCe6k+AKxGdfb1dfOvt7LXdmKIh5DtFK5B4s/oiyK7oFngughlyonCIiOa0V0pSVOth9K1UbjTqgEQJbPzPfneVdFtYlq3nQjMceHc6ZL+opsAAey/TdrL9Qa2/b+XQUNlf+73b7p1/k9O1QAluv4AUx00ySypzoR6H3Ig5mmQbNDIBMRdeqrjOO2GiGWTLlf9G1weDe+awfP+I0yt4yM6AwlqEWrIs/HgPpjeDbkXFjD8RmHp9D1z+debFrooCW5+mzZRCIgG2ypNmoP7HJrsX69K8TSOlReqeeAWBmowpxN2OAzkt91FkG4JR9ZlNlI+MFIhiNhqDmV0eT2trFS4XZEAW4r4Mw68ESHEoZ8cUJeGkay X-Forefront-Antispam-Report: CIP:216.228.117.161; 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New HCA capabilities indicating GENEVE TLV sample is supported. 2. New fields in "mlx5_ifc_geneve_tlv_option_bits" structure. Signed-off-by: Michael Baum --- drivers/common/mlx5/mlx5_devx_cmds.c | 18 ++++++++++++++++-- drivers/common/mlx5/mlx5_devx_cmds.h | 9 +++++++-- drivers/common/mlx5/mlx5_prm.h | 15 +++++++++++---- 3 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 9855a97bf4..674130c11f 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -968,6 +968,10 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, max_geneve_tlv_options); attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, max_geneve_tlv_option_data_len); + attr->geneve_tlv_option_offset = MLX5_GET(cmd_hca_cap, hcattr, + geneve_tlv_option_offset); + attr->geneve_tlv_sample = MLX5_GET(cmd_hca_cap, hcattr, + geneve_tlv_sample); attr->query_match_sample_info = MLX5_GET(cmd_hca_cap, hcattr, query_match_sample_info); attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); @@ -2883,11 +2887,21 @@ mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, MLX5_CMD_OP_CREATE_GENERAL_OBJECT); MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); - MLX5_SET(geneve_tlv_option, opt, option_class, - rte_be_to_cpu_16(attr->option_class)); MLX5_SET(geneve_tlv_option, opt, option_type, attr->option_type); MLX5_SET(geneve_tlv_option, opt, option_data_length, attr->option_data_len); + if (attr->option_class_ignore) + MLX5_SET(geneve_tlv_option, opt, option_class_ignore, + attr->option_class_ignore); + else + MLX5_SET(geneve_tlv_option, opt, option_class, + rte_be_to_cpu_16(attr->option_class)); + if (attr->offset_valid) { + MLX5_SET(geneve_tlv_option, opt, sample_offset_valid, + attr->offset_valid); + MLX5_SET(geneve_tlv_option, opt, sample_offset, + attr->sample_offset); + } geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, sizeof(out)); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 78337dff17..3f294e8f04 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -212,8 +212,10 @@ struct mlx5_hca_attr { uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; uint16_t lro_min_mss_size; uint32_t flex_parser_protocols; - uint32_t max_geneve_tlv_options; - uint32_t max_geneve_tlv_option_data_len; + uint32_t max_geneve_tlv_options:8; + uint32_t max_geneve_tlv_option_data_len:5; + uint32_t geneve_tlv_sample:1; + uint32_t geneve_tlv_option_offset:1; uint32_t hairpin:1; uint32_t log_max_hairpin_queues:5; uint32_t log_max_hairpin_wq_data_sz:5; @@ -674,6 +676,9 @@ struct mlx5_devx_geneve_tlv_option_attr { uint32_t option_class:16; uint32_t option_type:8; uint32_t option_data_len:5; + uint32_t option_class_ignore:1; + uint32_t offset_valid:1; + uint32_t sample_offset:8; }; /* mlx5_devx_cmds.c */ diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 9e22dce6da..59643a8788 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1849,7 +1849,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 num_of_uars_per_page[0x20]; u8 flex_parser_protocols[0x20]; u8 max_geneve_tlv_options[0x8]; - u8 reserved_at_568[0x3]; + u8 geneve_tlv_sample[0x1]; + u8 geneve_tlv_option_offset[0x1]; + u8 reserved_at_56a[0x1]; u8 max_geneve_tlv_option_data_len[0x5]; u8 flex_parser_header_modify[0x1]; u8 reserved_at_571[0x2]; @@ -3416,16 +3418,21 @@ struct mlx5_ifc_virtio_q_counters_bits { struct mlx5_ifc_geneve_tlv_option_bits { u8 modify_field_select[0x40]; - u8 reserved_at_40[0x18]; + u8 reserved_at_40[0x8]; + u8 sample_offset[0x8]; + u8 sample_id_valid[0x1]; + u8 sample_offset_valid[0x1]; + u8 option_class_ignore[0x1]; + u8 reserved_at_53[0x5]; u8 geneve_option_fte_index[0x8]; u8 option_class[0x10]; u8 option_type[0x8]; u8 reserved_at_78[0x3]; u8 option_data_length[0x5]; - u8 reserved_at_80[0x180]; + u8 geneve_sample_field_id[0x20]; + u8 reserved_at_a0[0x160]; }; - enum mlx5_ifc_rtc_update_mode { MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH = 0x0, MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET = 0x1,