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Thu, 25 Jan 2024 05:31:22 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Dariusz Sosnowski , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v2 14/23] net/mlx5: add API to expose GENEVE option FW information Date: Thu, 25 Jan 2024 15:30:34 +0200 Message-ID: <20240125133043.575860-15-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240125133043.575860-1-michaelba@nvidia.com> References: <20231203112543.844014-1-michaelba@nvidia.com> <20240125133043.575860-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3A:EE_|DM4PR12MB6229:EE_ X-MS-Office365-Filtering-Correlation-Id: 90f6fb49-036a-472f-08e3-08dc1da9f1bd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: atFbsAvAx5Lb0vxVmByh2c6EolV21HFMfoyiXNKISIg7d+aEse5Ca0Le5942Oz18gL/53g0J5vpFi4bkt/BONw/hqfUMjm2capeMB9iWcxct7QZtX7ojHU75ZEj9ltirnGYbarFjcKuQ7i6yyZSmTnddkvChaomthsoxOHaXc16Newh0SXadJemRYCaBjVcPn9TzjhIb1srIIM5qldqljsenHvpYFq9a2JwRmo4FXIidM5jvo62CFWHjKaIs7ejRuTVd5Ku2yieaK8g1wf0UuFPvZOsEoEcucdhzQ1+Kyf2Zf1PWm7QC26s6QShwq8JDs8miEdJaqQJKdbSuHU1p3ijMgeNWT27tx3jzna9077Ef8wPsF9vLXF80p6i2Z7AvJRxjLitNkxfAjp+ounzHb8P/pGhiN67BUhWT7Zwjd/ChtNPI3Y2XUTR5AZ/f3zDW+nI7KQxEilOutQvv/TfwUoSJ0HxOIF9hO/EJ0R7SymRhEK6Qb8SpzS0h/iI5om9grKpZW0pqEFJrYHLM9YM9+Onl3gxss7pnaLeNgLfgG/y8PfT4K2qwcLSko4QXMq8hSuZu/KVOuEvgkVO1YRtDoGH3yCeoKlSrJDZEdGU9RxI/oaGZD1kPuOQKCMuzUWGnIcq9hDqNpy6wRDroXtYyI7gcl5uTmLfr0OFDmMG2Bf2TwjPB2sQ/kjoijwikn1wjLBU9Qo9G64FVNJEbEiNHfx/+8CtTN478HgIS8ULntz+obLEb31SkwTUN4N/tJIXJ X-Forefront-Antispam-Report: CIP:216.228.118.232; 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Signed-off-by: Michael Baum Acked-by: Suanming Mou --- drivers/net/mlx5/mlx5_flow.h | 28 +++++++++ drivers/net/mlx5/mlx5_flow_geneve.c | 94 +++++++++++++++++++++++++++++ 2 files changed, 122 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 4bf9ed7e4d..14806fa78e 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1772,6 +1772,34 @@ flow_hw_get_reg_id_from_ctx(void *dr_ctx, return REG_NON; } +/** + * Get GENEVE TLV option FW information according type and class. + * + * @param[in] dr_ctx + * Pointer to HW steering DR context. + * @param[in] type + * GENEVE TLV option type. + * @param[in] class + * GENEVE TLV option class. + * @param[out] hl_ok_bit + * Pointer to header layout structure describing OK bit FW information. + * @param[out] num_of_dws + * Pointer to fill inside the size of 'hl_dws' array. + * @param[out] hl_dws + * Pointer to header layout array describing data DWs FW information. + * @param[out] ok_bit_on_class + * Pointer to an indicator whether OK bit includes class along with type. + * + * @return + * 0 on success, negative errno otherwise and rte_errno is set. + */ +int +mlx5_get_geneve_hl_data(const void *dr_ctx, uint8_t type, uint16_t class, + struct mlx5_hl_data ** const hl_ok_bit, + uint8_t *num_of_dws, + struct mlx5_hl_data ** const hl_dws, + bool *ok_bit_on_class); + void * mlx5_geneve_tlv_parser_create(uint16_t port_id, const struct rte_pmd_mlx5_geneve_tlv tlv_list[], diff --git a/drivers/net/mlx5/mlx5_flow_geneve.c b/drivers/net/mlx5/mlx5_flow_geneve.c index f23fb31aa0..2d593b70ba 100644 --- a/drivers/net/mlx5/mlx5_flow_geneve.c +++ b/drivers/net/mlx5/mlx5_flow_geneve.c @@ -58,6 +58,100 @@ struct mlx5_geneve_tlv_options { RTE_ATOMIC(uint32_t) refcnt; }; +/** + * Check if type and class is matching to given GENEVE TLV option. + * + * @param type + * GENEVE option type. + * @param class + * GENEVE option class. + * @param option + * Pointer to GENEVE TLV option structure. + * + * @return + * True if this type and class match to this option, false otherwise. + */ +static inline bool +option_match_type_and_class(uint8_t type, uint16_t class, + struct mlx5_geneve_tlv_option *option) +{ + if (type != option->type) + return false; + if (option->class_mode == 1 && option->class != class) + return false; + return true; +} + +/** + * Get GENEVE TLV option matching to given type and class. + * + * @param priv + * Pointer to port's private data. + * @param type + * GENEVE option type. + * @param class + * GENEVE option class. + * + * @return + * Pointer to option structure if exist, NULL otherwise and rte_errno is set. + */ +static struct mlx5_geneve_tlv_option * +mlx5_geneve_tlv_option_get(const struct mlx5_priv *priv, uint8_t type, + uint16_t class) +{ + struct mlx5_geneve_tlv_options *options; + uint8_t i; + + if (priv->tlv_options == NULL) { + DRV_LOG(ERR, + "Port %u doesn't have configured GENEVE TLV options.", + priv->dev_data->port_id); + rte_errno = EINVAL; + return NULL; + } + options = priv->tlv_options; + MLX5_ASSERT(options != NULL); + for (i = 0; i < options->nb_options; ++i) { + struct mlx5_geneve_tlv_option *option = &options->options[i]; + + if (option_match_type_and_class(type, class, option)) + return option; + } + DRV_LOG(ERR, "TLV option type %u class %u doesn't exist.", type, class); + rte_errno = ENOENT; + return NULL; +} + +int +mlx5_get_geneve_hl_data(const void *dr_ctx, uint8_t type, uint16_t class, + struct mlx5_hl_data ** const hl_ok_bit, + uint8_t *num_of_dws, + struct mlx5_hl_data ** const hl_dws, + bool *ok_bit_on_class) +{ + uint16_t port_id; + + MLX5_ETH_FOREACH_DEV(port_id, NULL) { + struct mlx5_priv *priv; + struct mlx5_geneve_tlv_option *option; + + priv = rte_eth_devices[port_id].data->dev_private; + if (priv->dr_ctx != dr_ctx) + continue; + /* Find specific option inside list. */ + option = mlx5_geneve_tlv_option_get(priv, type, class); + if (option == NULL) + return -rte_errno; + *hl_ok_bit = &option->hl_ok_bit; + *hl_dws = option->match_data; + *num_of_dws = option->match_data_size; + *ok_bit_on_class = !!(option->class_mode == 1); + return 0; + } + DRV_LOG(ERR, "DR CTX %p doesn't belong to any DPDK port.", dr_ctx); + return -EINVAL; +} + /** * Create single GENEVE TLV option sample. *