From patchwork Mon Feb 26 13:18:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 137210 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9903743BED; Mon, 26 Feb 2024 14:19:30 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2EB1542E35; Mon, 26 Feb 2024 14:19:20 +0100 (CET) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2045.outbound.protection.outlook.com [40.107.244.45]) by mails.dpdk.org (Postfix) with ESMTP id 052B942E2E for ; Mon, 26 Feb 2024 14:19:18 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FOH6pg7W0aiKKfbw5jzEt1kxoZVjcI3Q+ruNkIRMYWYIy+A9JfcseAh5xnpMEPTz9xYnGxvAuEoYo7QFJC/jPObxi/J08xnS4DOoTYGEfg1+LhGGRv+rnurxwLiF5Pr74zaw7o7+N6Xoh1CdgX/kJUV5vBjEROPe9GmD9j8BOEatIDXXr0nz0GuzD6GBqLY4a62lXp14S3a//mUyiyiiOwBjUCZNU5irMWqzZ824E/eQbCxEZTkCn4cui9IamHw8ep/mLO3H3Z0OYLx2KsICyMhlfriwZU7ZXTfz5LFo5rSR1w6CQKvfONXl0uYXzGF9/GWTOywkT4kt9OanIbew8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6gkzmxhvkLvsSugaaFnJBG6CK8JXqbzq4cTbzPRbPyM=; b=mDdS7Fy9JJ+1akZluyF5jtKWDGdJwK0EpbmjqWLPMJJjO9G0pYjjXDg6RMoVcfeD7YWEDFrw4vy1qNIebpoDxDgahlKsRQzYyXo1CgExh5Qp5RyCsZGao43fY7H3Bzeuu4MO7TrBtMW5iwiiFJDeTX7Xua37BWBeGzuZ2cVSjcUMlVPflZHn6fnEwDz22IjEXWd6G8IF0MoQqdRlstYmr81tzyYl2MVZ1Sx/s2ZbagKk7PI6pN/kY4xKGqJDM9ign4JKyf8QK/b4cZ8K27YvR+uDwuaJCn85SmEsxIkVa90qmKsTXnEoJF8LwahvOSeFy1tmVn+FO2zFzXksSiXj1w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6gkzmxhvkLvsSugaaFnJBG6CK8JXqbzq4cTbzPRbPyM=; b=cJhDn56Slmwaobg9W7ifCQ2+SuanSUzT12oN9Qc4q5wxiRSB/eDJny4mkm4aQmNp2Y9NnLMKJL3YrEDHLRp/m2ToHjQWi2VpYKXp+Ht8ZVC194XmtjZ7nxH0SPUWUXYc3lgLcqoPdhRl8RvSLbkkfj5tTvuJNQkMX+7PX0zex4G49g47mwMuJHpgYaXsrPy1893n8WOlhsuDNBd9xo9+pgdI5oFcSxvipMM77sSHeB/8VSfpOh0a+rWOl1mPqpem15IJkCQpkUOvBFnoYyhEIWItF11V3HWFf6ip7OJUGrENoRfi0hv7IfyT1UbAWwWwTcuhjVKY1+oXRWovCDf7fA== Received: from CH2PR14CA0009.namprd14.prod.outlook.com (2603:10b6:610:60::19) by BL1PR12MB5780.namprd12.prod.outlook.com (2603:10b6:208:393::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.36; Mon, 26 Feb 2024 13:19:15 +0000 Received: from DS3PEPF000099E1.namprd04.prod.outlook.com (2603:10b6:610:60:cafe::62) by CH2PR14CA0009.outlook.office365.com (2603:10b6:610:60::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.49 via Frontend Transport; Mon, 26 Feb 2024 13:19:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by DS3PEPF000099E1.mail.protection.outlook.com (10.167.17.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Mon, 26 Feb 2024 13:19:14 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 26 Feb 2024 05:19:02 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 26 Feb 2024 05:19:02 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12 via Frontend Transport; Mon, 26 Feb 2024 05:19:00 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v7 3/3] net/mlx5/hws: add compare ESP sequence number support Date: Mon, 26 Feb 2024 15:18:48 +0200 Message-ID: <20240226131848.2982242-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226131848.2982242-1-michaelba@nvidia.com> References: <20240226130324.2981025-1-michaelba@nvidia.com> <20240226131848.2982242-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E1:EE_|BL1PR12MB5780:EE_ X-MS-Office365-Filtering-Correlation-Id: de545504-03d8-425d-6d87-08dc36cd8782 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sUHzOLkR/cltx9qkMh7bKWyoxpf4nxAui6PHfg+rjpmrLAdOOVnPLzZrO6TeFNOKB5drBn0sK0TsEgLuecHquo8CjmEuHN6RDCSOpbrD54hnwq14NKK0QQg2mZLrMD9N9SdUOn3/ue6BXpd6QRF4GQjv2nu/mdu0vGar2aZC7r8uQmb5oVSkv2+7Qts50GppdG/p7ESzVoJ/FiojK+3y/jcuiw7WmeaRzIJd+X/ExP7JFi7mHwUf0DnBy+UvEjD0Hl3s+CVm/So1btMs4ZTXebHPdKJvu0vXFp3d/koIoS8+9QGM2sfYx30hYzT53vDqeKTXgRGva81+x3t+jHkRojlZA40WXFYb2UkWd+lAvgD1lSQJILpIGdUrQpzvA0wQyp1weBE9Ve7UoYQ6dyV6Q50msLoBVR7YqnuCYyLa3BI+5HcjkbOT513/eE4nFSuXmMpvAcN5deXwBIGapqigORC7TEwoGH6eF+LbzW1htp4dHODFtrAsDW/bJWYTKqAsmdQ6uEQci319i914Rff6xHf9r1+crJEX+LQxVnZXs4bh/RmXTzyetAdT8Wg0re17RbvqbmnvqjkTmMuLT9IQDOaFGjxthriT9oRmcZvISbcmFDE8XphjMmeW+yUKB+hmZWOHp1mvxXyV2tk6cYVD2Csjp8ijxBwJws3vBI3MFUIqv9cz8q8WhhaKOLbNAzNBP3LfEeYcqPk6M88qE8B92NZSxfl1GcvTEP2Qtny49+NZFBEXARSSCrGWeZCiTaOZ X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2024 13:19:14.8185 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de545504-03d8-425d-6d87-08dc36cd8782 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5780 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for compare item with "RTE_FLOW_FIELD_ESP_SEQ_NUM" field. Signed-off-by: Michael Baum Acked-by: Suanming Mou --- doc/guides/nics/mlx5.rst | 1 + drivers/net/mlx5/hws/mlx5dr_definer.c | 22 ++++++++++++++++++++-- drivers/net/mlx5/mlx5_flow_hw.c | 3 +++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index c0a5768117..d7bf81161e 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -434,6 +434,7 @@ Limitations - Only single item is supported per pattern template. - Only 32-bit comparison is supported or 16-bits for random field. - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``, + ``RTE_FLOW_FIELD_ESP_SEQ_NUM``, ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``. - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field. - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 45e5bc5a61..c1508e6b53 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -424,10 +424,20 @@ mlx5dr_definer_compare_base_value_set(const void *item_spec, value = (const uint32_t *)&b->value[0]; - if (a->field == RTE_FLOW_FIELD_RANDOM) + switch (a->field) { + case RTE_FLOW_FIELD_RANDOM: *base = htobe32(*value << 16); - else + break; + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: *base = htobe32(*value); + break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + *base = *value; + break; + default: + break; + } MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1); } @@ -2930,6 +2940,14 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, fc->compare_idx = dw_offset; DR_CALC_SET_HDR(fc, random_number, random_number); break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + DR_CALC_SET_HDR(fc, ipsec, sequence_number); + break; default: DR_LOG(ERR, "%u field is not supported", f->field); goto err_notsup; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index f31ba2df2b..531c90e0ee 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6729,6 +6729,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, switch (arg_field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; case RTE_FLOW_FIELD_RANDOM: if (base_field == RTE_FLOW_FIELD_VALUE) @@ -6747,6 +6748,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: case RTE_FLOW_FIELD_VALUE: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; default: return rte_flow_error_set(error, ENOTSUP, @@ -6763,6 +6765,7 @@ flow_hw_item_compare_width_supported(enum rte_flow_field_id field) switch (field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: return 32; case RTE_FLOW_FIELD_RANDOM: return 16;